Abstract: An improved apparatus for annealing an ion-implanted semiconductor sample duces the deleterious side effects otherwise associated with the process. A semiconductor sample, fabricated, for example, from indium phosphide or gallium arsenide, is set upon the fingers of a carrier which is displaced to the interior of an elongate furnace having its internal temperature maintained at the proper annealing temperature. Next, the fingers are rotated and the sample is placed on a number of razor blade-like edges extending up from an internal rack. The carrier is withdrawn and the sample is quickly brought to the annealing temperature for the precise period of time usually no more than 20 seconds. After the exact annealing period, the carrier is reintroduced and the fingers are rotated to lift the sample from the rack and the sample is withdrawn.

Abstract: A method for annealing semiconductor samples, especially following ion-implantation of semiconductor samples is disclosed. A furnace on a set of rails is passed over the semiconductor sample which is supported on a stationary wire basket made of low thermal mass, fine tungsten wire. The furnace temperature may be about 5.degree. above the desired anneal temperature of the semiconductor sample such that the sample temperature rises to within a few degrees of the furnace temperature within seconds. Utilizing the moveable furnace insures uniform heating without elaborate temperature control or expensive beam generating equipment.The apparatus and process of the present invention are utilized for rapid annealing of ion-implanted indium phosphide semiconductors within 10 to 30 seconds and at temperatures of approximately 700.degree. C., thereby eliminating undesired and damaging movement of impurities within the ion-implanted InP.

Abstract: A field effect transistor comprises a diamond substrate which has a p-type ion implanted region coterminous with a surface of the diamond substrate, wherein the ion implanted region has a hole concentration in the range of 1.times.10.sup.15 to 1.times.10.sup.17 holes/cm.sup.2, and a hole mobility equal to or greater than 1 cm.sup.2 /V-sec; spaced apart source and drain electrodes formed over the p-type ion implanted region on the surface of the diamond substrate; an electrically insulating material formed over the p-type ion implanted region on the surface of the diamond substrate between the source and drain electrodes; and a gate electrode formed on the surface of the insulating material.