Abstract: Channel carrier mobility is increased by reducing gate/gate dielectric interface roughness, thereby reducing surface scattering. Embodiments include depositing a layer of silicon by selective epitaxy prior to gate oxide formation to provide a substantially atomically smooth surface resulting in a smoother interface between the gate polysilicon and silicon oxide after oxidation.

Abstract: A method of manufacturing a flash memory device with a controllable amount of gate edge lifting including etching the ends of the tunnel oxide forming a cavity at each end of the tunnel oxide and anisotropically depositing and etching an oxide to form spacers on the sides of the gate stack. The spacers have a predetermined thickness that controls the amount of gate edge lifting. The predetermined thickness is determined during a characterization procedure that can be a computer modeling procedure or it can be determined empirically.

Abstract: A field effect transistor (300) having a source region (304) and a drain region (306) includes a source side halo region (332) formed at a junction between the source region and a channel region to substantially interrupt off state leakage current. The source side halo region is formed by implanting (408) first doping ions near the surface at the source side of the channel and implanting (410) second doping ions deeper in the channel, near the depth of a source extension (322). In this manner, optimization of leakage current of the field effect transistor is made independent of the drive current of the field effect transistor.

Abstract: A method of reducing the gate resistance in a semiconductor device forms a gate in the semiconductor device followed by the creation of a silicide region on top of the gate. During the initial formation of the silicide region on the gate, formation of silicide on source/drain areas of the semiconductor device is prevented by a shielding material. The shielding material is then removed and additional silicide is created, forming silicide regions on the source/drains and increasing the thickness of the silicide over the gate, thereby lowering the gate resistance.

Abstract: The method of fabricating the semi-conductor device includes forming a center dielectric region on a substrate. The center dielectric region has a first thickness and the substrate includes a first conductive material. Then, a first plurality of spacers is formed near the center dielectric region. A second conductive material is implanted into the substrate using the first plurality of spacers for alignment. The second conductive material form sources/drains the first plurality of spacers are then removed and a dielectric layer is formed over the substrate and the source/drain regions. The dielectric layer has a second thickness that is less than the first thickness. A second plurality of spacers is formed near the center dielectric region. The second plurality of spacers are conductive and have a third thickness that is substantially equal to the difference of the first and second thickness'. A gate dielectric layer is formed over the substrate, center dielectric region, and second plurality of spacers.

Abstract: A method of manufacturing a flash memory device in which minimal gate edge lifting is accomplished by minimally oxidizing the gate stack and exposed surface of the substrate, anisotropically etching the layer of oxide from the substrate, forming a doped solid source material on portions of the substrate in which source regions are to be formed and diffusing the dopants from the solid source material into the substrate.

Abstract: A method of manufacturing a flash memory device in which minimal gate edge lifting is accomplished by etching a portion of the ends of the layer of tunnel oxide forming cavities, forming silicon nitride plugs in the cavities and forming a layer of oxide on the surface of the flash memory device wherein the silicon nitride plugs minimize gate edge lifting.

Abstract: A method for manufacturing a field effect transistor (100) includes steps of forming a gate stack (102) on the surface (114) of a semiconductor substrate (108), and defining source/drain regions (104, 106) on either side of the gate stack and a channel region (130) under the gate stack. The channel region has one end (132) proximate a first source/drain region and another end (134) proximate a second source/drain region. The method further includes forming a masking layer (174) on the surface of the semiconductor substrate. The masking layer has a nominal alignment position and a misalignment tolerance. The method still further includes implanting doping ions in the semiconductor substrate to asymmetrically dope the field effect transistor, including selecting a tilt angle and a rotation angle (B, D, F, H) sufficient to ensure shadowing of one end of the channel region from implantation of the doping ions.

Abstract: A method of manufacturing a flash memory device with blunted corners of the floating gate. The blunted corners of the floating gate allow a reduction in the required gate edge lifting that is designed into flash memory design and allows a shortening of the flash memory device to increase the density of flash memory devices that can be formed in a given area.