Patents by Inventor Carl Thomas

Carl Thomas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250211359
    Abstract: A dense wave division multiplex (DWDM) receiver includes receiver lanes each configured to detect signals encoded in a different electromagnetic frequency band. The DWDM receiver applies a clock signal received on a variable one of the receiver lanes to lock a frequency of an injection locked oscillator (ILO) of a clock distribution network, and receiver lanes that are configured to receive data signals generate resonance on the clock distribution network. The resonant signal from the clock distribution network is applied to sample the received data signals.
    Type: Application
    Filed: December 21, 2023
    Publication date: June 26, 2025
    Applicant: NVIDIA Corp.
    Inventors: Sanquan Song, Nikola Nedovic, Thomas Hastings Greer III, Carl Thomas Gray
  • Publication number: 20250189251
    Abstract: A ram accelerator for accelerating a projectile is provided. The ram accelerator includes a first tube body having a first projectile bore, a second tube body having a second projectile bore axially aligned with the first projectile bore, and a baffle positioned between and operably coupling the first and second tube bodies. The baffle can have an annular baffle wall defining a central bore that is axially aligned with the first and second projectile bores, and a chamber arranged adjacent to the annular baffle wall. The chamber can extend radially outward from the central bore and the annular baffle wall can be configured to sweep a combustion wave relative to the projectile to prevent the combustion wave from traveling ahead of the projectile, leading to an unstart mechanism of the projectile in the ram accelerator.
    Type: Application
    Filed: March 10, 2023
    Publication date: June 12, 2025
    Applicant: University of Washington
    Inventors: Carl Thomas Knowlen, Andrew Jason Higgins, Brian Leege
  • Patent number: 12272143
    Abstract: A surveillance system for detecting and/or characterizing movement of a monitored infrastructure. An improved compromise between tight zone surveillance and number of false alarms is provided by an improved control of a 3D surveillance device. An input functionality is provided for a user to define a 3D subzone within a 3D environment model. A change functionality allows the user to generate a redefined subzone by dragging one of the corner points of the 3D subzone to a different position within a 3D visualization of the 3D environment model, whereby the shape of the 3D subzone is distorted. The input functionality and the change functionality are used to provide to the 3D surveillance device spatial parameters associated with the redefined subzone and the 3D surveillance device is caused to generate an action in case a movement within the redefined subzone is detected by means of the 3D measurement data.
    Type: Grant
    Filed: January 5, 2023
    Date of Patent: April 8, 2025
    Assignee: LEICA GEOSYSTEMS AG
    Inventors: Markus Ribi, Sandra Tobler, Adam Bajric, Carl-Thomas Schneider
  • Publication number: 20250105734
    Abstract: Power delivery systems for integrated circuits that include a first metal path traversing first metal layers from a global power domain supply to a voltage regulator, a second metal path traversing second metal layers from a local power domain supply to the voltage regulator, and a third metal path traversing third metal layers from the local power domain supply to an integrated circuit. Electrical isolation gaps are formed between the first metal layers, the second metal layers, and the third metal layers.
    Type: Application
    Filed: September 24, 2024
    Publication date: March 27, 2025
    Applicant: NVIDIA Corp.
    Inventors: Siddharth Saxena, Sudhir Shrikantha Kudva, Miguel Rodriguez, Vijay Srinivasan, Tezaswi Raja, Carl Thomas Gray, Santosh Santosh
  • Publication number: 20250052437
    Abstract: A rotary mister is described. The rotary mister may include a rotary movement element that is able to rotate about an axis (e.g., a linear member of the rotary mister). The rotary mister may include a fluid supply and/or output element (e.g., conduit or tubing, connectors, nozzles, etc.). The rotary mister may include a fluid dispersion element (e.g., a fan). The rotary mister of some embodiments may utilize a low-pressure supply, such as a standard water supply at standard pressure. An extended coverage area may be provided by a tube fan that rotates about the axis point.
    Type: Application
    Filed: August 5, 2024
    Publication date: February 13, 2025
    Applicant: Right Testing Labs
    Inventors: Stephen Scott Parkhurst, Drew Matthew Mersereau, Carl Thomas Archbold
  • Patent number: 12223201
    Abstract: A hierarchical network enables access for a stacked memory system including or more memory dies that each include multiple memory tiles. The processor die includes multiple processing tiles that are stacked with the one or more memory die. The memory tiles that are vertically aligned with a processing tile are directly coupled to the processing tile and comprise the local memory block for the processing tile. The hierarchical network provides access paths for each processing tile to access the processing tile's local memory block, the local memory block coupled to a different processing tile within the same processing die, memory tiles in a different die stack, and memory tiles in a different device. The ratio of memory bandwidth (byte) to floating-point operation (B:F) may improve 50× for accessing the local memory block compared with conventional memory. Additionally, the energy consumed to transfer each bit may be reduced by 10×.
    Type: Grant
    Filed: February 9, 2024
    Date of Patent: February 11, 2025
    Assignee: NVIDIA Corporation
    Inventors: William James Dally, Carl Thomas Gray, Stephen W. Keckler, James Michael O'Connor
  • Publication number: 20240411709
    Abstract: Embodiments of the present disclosure relate to application partitioning for locality in a stacked memory system. In an embodiment, one or more memory dies are stacked on the processor die. The processor die includes multiple processing tiles and each memory die includes multiple memory tiles. Vertically aligned memory tiles are directly coupled to and comprise the local memory block for a corresponding processing tile. An application program that operates on dense multi-dimensional arrays (matrices) may partition the dense arrays into sub-arrays associated with program tiles. Each program tile is executed by a processing tile using the processing tile's local memory block to process the associated sub-array. Data associated with each sub-array is stored in a local memory block and the processing tile corresponding to the local memory block executes the program tile to process the sub-array data.
    Type: Application
    Filed: August 21, 2024
    Publication date: December 12, 2024
    Inventors: William James Dally, Carl Thomas Gray, Stephen W. Keckler, James Michael O'Connor
  • Patent number: 12146531
    Abstract: A clutch assembly or module having multiple one-way clutches, each clutch operates independently of the others to control torque transmission to and from a common or shared notch plate. The assembly or module also controls rotation, including the direction thereof, of the common or shared notch plate. Depending upon the position of each one-way clutch, multiple modes of torque transfer and common or shared notch plate rotation can be achieved.
    Type: Grant
    Filed: February 17, 2023
    Date of Patent: November 19, 2024
    Assignee: Means Industries, Inc.
    Inventor: Carl Thomas Beiser
  • Patent number: 12131800
    Abstract: PUF cells utilizing a dual-interlocking scheme demonstrating improved noise immunity and stability across different V/T conditions and different uses over time in noisy environments. The PUF cell may be advantageously utilized in conjunction with error detection techniques that screen out unstable cells. A set of such PUF cells utilized to generate a device-specific bit pattern, for example a master key.
    Type: Grant
    Filed: November 16, 2022
    Date of Patent: October 29, 2024
    Assignee: NVIDIA Corp.
    Inventors: Mahmut Ersin Sinangil, Sudhir Shrikantha Kudva, Nikola Nedovic, Carl Thomas Gray
  • Publication number: 20240333595
    Abstract: Devices, computer-readable media, and methods for automatically configuring network elements in multi-vendor and multi-domain topologies. In one example, a method includes determining a need of a communications network, where a topology of the communications network includes a plurality of network functions from at least two different vendors, predicting a subset of the plurality of network functions and respective configuration parameter values for network functions in the subset, that are expected to support the need of the communications network, and modifying the configurations of the network functions in the subset to reflect the respective configuration parameter values.
    Type: Application
    Filed: June 10, 2024
    Publication date: October 3, 2024
    Inventors: Mritunjay Pandey, Subhash Kapoor, Carl Thomas, Somnath Mallick, Lalena Aria, Donald Charles Jeffery, Saurav Paira
  • Patent number: 12099453
    Abstract: Embodiments of the present disclosure relate to application partitioning for locality in a stacked memory system. In an embodiment, one or more memory dies are stacked on the processor die. The processor die includes multiple processing tiles and each memory die includes multiple memory tiles. Vertically aligned memory tiles are directly coupled to and comprise the local memory block for a corresponding processing tile. An application program that operates on dense multi-dimensional arrays (matrices) may partition the dense arrays into sub-arrays associated with program tiles. Each program tile is executed by a processing tile using the processing tile's local memory block to process the associated sub-array. Data associated with each sub-array is stored in a local memory block and the processing tile corresponding to the local memory block executes the program tile to process the sub-array data.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: September 24, 2024
    Assignee: NVIDIA Corporation
    Inventors: William James Dally, Carl Thomas Gray, Stephen W. Keckler, James Michael O'Connor
  • Patent number: 12091794
    Abstract: Systems and methods for producing printed goods from textile material to address shortcoming of existing approaches for article production. According to the systems and methods described herein, the harvested and woven cotton may be shipped directly to garment decorators who may perform all remaining steps to provide customers with finished goods. As such, the systems and methods herein may eliminate the steps of the blank goods trade and current manufacturing processes.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: September 17, 2024
    Inventor: Carl Thomas Ingling
  • Patent number: 12050115
    Abstract: A test manager and media interface (TMMI) may manage testing procedures associated with a test such as a product test, capture media and sensor data associated with the test, and generate a synchronized multimedia presentation based on the captured media and sensor data. A TMMI include: a test environment having: a test applicator for applying a test stimulus to an item under test; a sensor that measures at least one test attribute; and a media capture element that captures media including video of the item under test. The TMMI may include a media interface that generates a graphical user interface including at least a portion of the media captured by the media capture element and the at least one attribute.
    Type: Grant
    Filed: June 1, 2021
    Date of Patent: July 30, 2024
    Assignee: Right Testing Labs
    Inventors: Stephen Scott Parkhurst, Drew Matthew Mersereau, Carl Thomas Archbold
  • Publication number: 20240211166
    Abstract: A hierarchical network enables access for a stacked memory system including or more memory dies that each include multiple memory tiles. The processor die includes multiple processing tiles that are stacked with the one or more memory die. The memory tiles that are vertically aligned with a processing tile are directly coupled to the processing tile and comprise the local memory block for the processing tile. The hierarchical network provides access paths for each processing tile to access the processing tile's local memory block, the local memory block coupled to a different processing tile within the same processing die, memory tiles in a different die stack, and memory tiles in a different device. The ratio of memory bandwidth (byte) to floating-point operation (B:F) may improve 50× for accessing the local memory block compared with conventional memory. Additionally, the energy consumed to transfer each bit may be reduced by 10×.
    Type: Application
    Filed: February 9, 2024
    Publication date: June 27, 2024
    Inventors: William James Dally, Carl Thomas Gray, Stephen W. Keckler, James Michael O'Connor
  • Publication number: 20240195695
    Abstract: Devices, computer-readable media, and methods for automatically configuring network elements in multi-vendor and multi-domain topologies. In one example, a method includes determining a need of a communications network, where a topology of the communications network includes a plurality of network functions from at least two different vendors, predicting a subset of the plurality of network functions and respective configuration parameter values for network functions in the subset, that are expected to support the need of the communications network, and modifying the configurations of the network functions in the subset to reflect the respective configuration parameter values.
    Type: Application
    Filed: December 13, 2022
    Publication date: June 13, 2024
    Inventors: Mritunjay Pandey, Subhash Kapoor, Carl Thomas, Somnath Mallick, Lalena Aria, Donald Charles Jeffery, Saurav Paira
  • Patent number: 12009983
    Abstract: Devices, computer-readable media, and methods for automatically configuring network elements in multi-vendor and multi-domain topologies. In one example, a method includes determining a need of a communications network, where a topology of the communications network includes a plurality of network functions from at least two different vendors, predicting a subset of the plurality of network functions and respective configuration parameter values for network functions in the subset, that are expected to support the need of the communications network, and modifying the configurations of the network functions in the subset to reflect the respective configuration parameter values.
    Type: Grant
    Filed: December 13, 2022
    Date of Patent: June 11, 2024
    Assignees: AT&T Intellectual Property I, L.P., AT&T Communications Services India Private Limited, AT&T Global Network Services (UK) B.V.
    Inventors: Mritunjay Pandey, Subhash Kapoor, Carl Thomas, Somnath Mallick, Lalena Aria, Donald Charles Jeffery, Saurav Paira
  • Publication number: 20240161800
    Abstract: PUF cells utilizing a dual-interlocking scheme demonstrating improved noise immunity and stability across different V/T conditions and different uses over time in noisy environments. The PUF cell may be advantageously utilized in conjunction with error detection techniques that screen out unstable cells. A set of such PUF cells utilized to generate a device-specific bit pattern, for example a master key.
    Type: Application
    Filed: November 16, 2022
    Publication date: May 16, 2024
    Applicant: NVIDIA Corp.
    Inventors: Mahmut Ersin Sinangil, Sudhir Shrikantha Kudva, Nikola Nedovic, Carl Thomas Gray
  • Patent number: 11977766
    Abstract: A hierarchical network enables access for a stacked memory system including or more memory dies that each include multiple memory tiles. The processor die includes multiple processing tiles that are stacked with the one or more memory die. The memory tiles that are vertically aligned with a processing tile are directly coupled to the processing tile and comprise the local memory block for the processing tile. The hierarchical network provides access paths for each processing tile to access the processing tile's local memory block, the local memory block coupled to a different processing tile within the same processing die, memory tiles in a different die stack, and memory tiles in a different device. The ratio of memory bandwidth (byte) to floating-point operation (B:F) may improve 50× for accessing the local memory block compared with conventional memory. Additionally, the energy consumed to transfer each bit may be reduced by 10×.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: May 7, 2024
    Assignee: NVIDIA Corporation
    Inventors: William James Dally, Carl Thomas Gray, Stephen W. Keckler, James Michael O'Connor
  • Patent number: 11784835
    Abstract: A circuit includes a set of multiple bit generating cells. One or more adjustable characterization circuits are coupled to inputs to the bit generating cells to affect the outputs of the bit generating cells. Based on the effect of the characterization circuit(s) on the outputs of the bit generating cells, a subset less than all of the bit generating cells is selected.
    Type: Grant
    Filed: September 21, 2021
    Date of Patent: October 10, 2023
    Assignee: NVIDIA CORP.
    Inventors: Sudhir Shrikantha Kudva, Nikola Nedovic, Carl Thomas Gray, Stephen G Tell
  • Publication number: 20230315651
    Abstract: Embodiments of the present disclosure relate to application partitioning for locality in a stacked memory system. In an embodiment, one or more memory dies are stacked on the processor die. The processor die includes multiple processing tiles and each memory die includes multiple memory tiles. Vertically aligned memory tiles are directly coupled to and comprise the local memory block for a corresponding processing tile. An application program that operates on dense multi-dimensional arrays (matrices) may partition the dense arrays into sub-arrays associated with program tiles. Each program tile is executed by a processing tile using the processing tile's local memory block to process the associated sub-array. Data associated with each sub-array is stored in a local memory block and the processing tile corresponding to the local memory block executes the program tile to process the sub-array data.
    Type: Application
    Filed: March 30, 2022
    Publication date: October 5, 2023
    Inventors: William James Dally, Carl Thomas Gray, Stephen W. Keckler, James Michael O'Connor