Abstract: A rotary mister is described. The rotary mister may include a rotary movement element that is able to rotate about an axis (e.g., a linear member of the rotary mister). The rotary mister may include a fluid supply and/or output element (e.g., conduit or tubing, connectors, nozzles, etc.). The rotary mister may include a fluid dispersion element (e.g., a fan). The rotary mister of some embodiments may utilize a low-pressure supply, such as a standard water supply at standard pressure. An extended coverage area may be provided by a tube fan that rotates about the axis point.

Abstract: A hierarchical network enables access for a stacked memory system including or more memory dies that each include multiple memory tiles. The processor die includes multiple processing tiles that are stacked with the one or more memory die. The memory tiles that are vertically aligned with a processing tile are directly coupled to the processing tile and comprise the local memory block for the processing tile. The hierarchical network provides access paths for each processing tile to access the processing tile's local memory block, the local memory block coupled to a different processing tile within the same processing die, memory tiles in a different die stack, and memory tiles in a different device. The ratio of memory bandwidth (byte) to floating-point operation (B:F) may improve 50× for accessing the local memory block compared with conventional memory. Additionally, the energy consumed to transfer each bit may be reduced by 10×.

Abstract: A system includes a robotic arm of a robotic device, an imaging device coupled to the robotic arm, and a processor configured to control movement of the robotic arm to move the imaging device along a preprogrammed measurement path of a transparency while prompting the imaging device to record images of localized portions of the transparency. The processor is configured to determine one or more localized transparency characteristics based on an analysis of the images of the localized portions.

Abstract: Embodiments of the present disclosure relate to application partitioning for locality in a stacked memory system. In an embodiment, one or more memory dies are stacked on the processor die. The processor die includes multiple processing tiles and each memory die includes multiple memory tiles. Vertically aligned memory tiles are directly coupled to and comprise the local memory block for a corresponding processing tile. An application program that operates on dense multi-dimensional arrays (matrices) may partition the dense arrays into sub-arrays associated with program tiles. Each program tile is executed by a processing tile using the processing tile's local memory block to process the associated sub-array. Data associated with each sub-array is stored in a local memory block and the processing tile corresponding to the local memory block executes the program tile to process the sub-array data.

Abstract: A clutch assembly or module having multiple one-way clutches, each clutch operates independently of the others to control torque transmission to and from a common or shared notch plate. The assembly or module also controls rotation, including the direction thereof, of the common or shared notch plate. Depending upon the position of each one-way clutch, multiple modes of torque transfer and common or shared notch plate rotation can be achieved.

Abstract: PUF cells utilizing a dual-interlocking scheme demonstrating improved noise immunity and stability across different V/T conditions and different uses over time in noisy environments. The PUF cell may be advantageously utilized in conjunction with error detection techniques that screen out unstable cells. A set of such PUF cells utilized to generate a device-specific bit pattern, for example a master key.

Abstract: Devices, computer-readable media, and methods for automatically configuring network elements in multi-vendor and multi-domain topologies. In one example, a method includes determining a need of a communications network, where a topology of the communications network includes a plurality of network functions from at least two different vendors, predicting a subset of the plurality of network functions and respective configuration parameter values for network functions in the subset, that are expected to support the need of the communications network, and modifying the configurations of the network functions in the subset to reflect the respective configuration parameter values.

Abstract: Embodiments of the present disclosure relate to application partitioning for locality in a stacked memory system. In an embodiment, one or more memory dies are stacked on the processor die. The processor die includes multiple processing tiles and each memory die includes multiple memory tiles. Vertically aligned memory tiles are directly coupled to and comprise the local memory block for a corresponding processing tile. An application program that operates on dense multi-dimensional arrays (matrices) may partition the dense arrays into sub-arrays associated with program tiles. Each program tile is executed by a processing tile using the processing tile's local memory block to process the associated sub-array. Data associated with each sub-array is stored in a local memory block and the processing tile corresponding to the local memory block executes the program tile to process the sub-array data.

Abstract: Systems and methods for producing printed goods from textile material to address shortcoming of existing approaches for article production. According to the systems and methods described herein, the harvested and woven cotton may be shipped directly to garment decorators who may perform all remaining steps to provide customers with finished goods. As such, the systems and methods herein may eliminate the steps of the blank goods trade and current manufacturing processes.

Abstract: A test manager and media interface (TMMI) may manage testing procedures associated with a test such as a product test, capture media and sensor data associated with the test, and generate a synchronized multimedia presentation based on the captured media and sensor data. A TMMI include: a test environment having: a test applicator for applying a test stimulus to an item under test; a sensor that measures at least one test attribute; and a media capture element that captures media including video of the item under test. The TMMI may include a media interface that generates a graphical user interface including at least a portion of the media captured by the media capture element and the at least one attribute.

Abstract: A hierarchical network enables access for a stacked memory system including or more memory dies that each include multiple memory tiles. The processor die includes multiple processing tiles that are stacked with the one or more memory die. The memory tiles that are vertically aligned with a processing tile are directly coupled to the processing tile and comprise the local memory block for the processing tile. The hierarchical network provides access paths for each processing tile to access the processing tile's local memory block, the local memory block coupled to a different processing tile within the same processing die, memory tiles in a different die stack, and memory tiles in a different device. The ratio of memory bandwidth (byte) to floating-point operation (B:F) may improve 50× for accessing the local memory block compared with conventional memory. Additionally, the energy consumed to transfer each bit may be reduced by 10×.

Abstract: Devices, computer-readable media, and methods for automatically configuring network elements in multi-vendor and multi-domain topologies. In one example, a method includes determining a need of a communications network, where a topology of the communications network includes a plurality of network functions from at least two different vendors, predicting a subset of the plurality of network functions and respective configuration parameter values for network functions in the subset, that are expected to support the need of the communications network, and modifying the configurations of the network functions in the subset to reflect the respective configuration parameter values.

Abstract: Devices, computer-readable media, and methods for automatically configuring network elements in multi-vendor and multi-domain topologies. In one example, a method includes determining a need of a communications network, where a topology of the communications network includes a plurality of network functions from at least two different vendors, predicting a subset of the plurality of network functions and respective configuration parameter values for network functions in the subset, that are expected to support the need of the communications network, and modifying the configurations of the network functions in the subset to reflect the respective configuration parameter values.

Abstract: PUF cells utilizing a dual-interlocking scheme demonstrating improved noise immunity and stability across different V/T conditions and different uses over time in noisy environments. The PUF cell may be advantageously utilized in conjunction with error detection techniques that screen out unstable cells. A set of such PUF cells utilized to generate a device-specific bit pattern, for example a master key.

Abstract: A hierarchical network enables access for a stacked memory system including or more memory dies that each include multiple memory tiles. The processor die includes multiple processing tiles that are stacked with the one or more memory die. The memory tiles that are vertically aligned with a processing tile are directly coupled to the processing tile and comprise the local memory block for the processing tile. The hierarchical network provides access paths for each processing tile to access the processing tile's local memory block, the local memory block coupled to a different processing tile within the same processing die, memory tiles in a different die stack, and memory tiles in a different device. The ratio of memory bandwidth (byte) to floating-point operation (B:F) may improve 50× for accessing the local memory block compared with conventional memory. Additionally, the energy consumed to transfer each bit may be reduced by 10×.

Abstract: A circuit includes a set of multiple bit generating cells. One or more adjustable characterization circuits are coupled to inputs to the bit generating cells to affect the outputs of the bit generating cells. Based on the effect of the characterization circuit(s) on the outputs of the bit generating cells, a subset less than all of the bit generating cells is selected.

Abstract: Embodiments of the present disclosure relate to application partitioning for locality in a stacked memory system. In an embodiment, one or more memory dies are stacked on the processor die. The processor die includes multiple processing tiles and each memory die includes multiple memory tiles. Vertically aligned memory tiles are directly coupled to and comprise the local memory block for a corresponding processing tile. An application program that operates on dense multi-dimensional arrays (matrices) may partition the dense arrays into sub-arrays associated with program tiles. Each program tile is executed by a processing tile using the processing tile's local memory block to process the associated sub-array. Data associated with each sub-array is stored in a local memory block and the processing tile corresponding to the local memory block executes the program tile to process the sub-array data.

Abstract: A hierarchical network enables access for a stacked memory system including or more memory dies that each include multiple memory tiles. The processor die includes multiple processing tiles that are stacked with the one or more memory die. The memory tiles that are vertically aligned with a processing tile are directly coupled to the processing tile and comprise the local memory block for the processing tile. The hierarchical network provides access paths for each processing tile to access the processing tile’s local memory block, the local memory block coupled to a different processing tile within the same processing die, memory tiles in a different die stack, and memory tiles in a different device. The ratio of memory bandwidth (byte) to floating-point operation (B:F) may improve 50x for accessing the local memory block compared with conventional memory. Additionally, the energy consumed to transfer each bit may be reduced by 10x.

Abstract: A mapper within a single-level memory system may facilitate memory localization to reduce the energy and latency of memory accesses within the single-level memory system. The mapper may translate a memory request received from a processor for implementation at a data storage entity, where the translating identifies a data storage entity and a starting location within the data storage entity where the data associated with the memory request is located. This data storage entity may be co-located with the processor that sent the request, which may enable the localization of memory and significantly improve the performance of memory usage by reducing an energy of data access and increasing data bandwidth.

Abstract: A clutch assembly or module having multiple one-way clutches, each clutch operates independently of the others to control torque transmission to and from a common or shared notch plate. The assembly or module also controls rotation, including the direction thereof, of the common or shared notch plate. Depending upon the position of each one-way clutch, multiple modes of torque transfer and common or shared notch plate rotation can be achieved.