Abstract: Data are error protected; dual memory control is utilized. From one memory control only write-in data are transmitted in addition to address and control signals; from the other memory control only control data is transmitted. In the first case they are inputted into the user data segment of a segmented memory, while in the second case, they are inputted into the control data segment of the memory from whence they are both included into the data check. Thereby, address errors may also be recognized.

Abstract: A circuit arrangement for an indirectly controlled exchange, in particular a telephone exchange, is provided with central control devices and, on the occurrence of a fault signal, for the retention of the operating states currently prevailing in the exchange, items of test data concerning the electrical states at specific test points are input into a memory, for which purpose the operating state prevailing in the exchange is temporarily maintained. The circuit arrangement includes two parallel operating control devices, each of which has a data bus and is additionally equipped with a status memory which serves to accommodate test data. The status memory includes an input which is connected to the respective data bus and an output which is connected to the data bus of the other control device. Each status memory is connected to at least one device which supplies fault signals and also to terminals which supply control signals of the control devices.