Abstract: The present disclosure pertains correcting linear interpolation errors. In one embodiment, a system comprises an input configured to receive the periodic signal at a first sampling rate and an output configured to provide an interpolated representation of the periodic signal at a second sampling rate. A linear interpolation subsystem may establish a ratio between the first sampling rate and the second sampling rate to determine a slip frequency. The linear interpolation subsystem creates an interpolated representation of the periodic signal based on the ratio. The interpolated representation of the periodic signal includes a deterministic error attributable to interpolation. A linear interpolation correction subsystem may correct the deterministic error attributable to the linear interpolation subsystem and create a corrected interpolated representation. An application interface subsystem may provide the corrected interpolated representation to an application.

Abstract: The present disclosure pertains correcting linear interpolation errors. In one embodiment, a system comprises an input configured to receive the periodic signal at a first sampling rate and an output configured to provide an interpolated representation of the periodic signal at a second sampling rate. A linear interpolation subsystem may establish a ratio between the first sampling rate and the second sampling rate to determine a slip frequency. The linear interpolation subsystem creates an interpolated representation of the periodic signal based on the ratio. The interpolated representation of the periodic signal includes a deterministic error attributable to interpolation. A linear interpolation correction subsystem may correct the deterministic error attributable to the linear interpolation subsystem and create a corrected interpolated representation. An application interface subsystem may provide the corrected interpolated representation to an application.

Abstract: An apparatus and method for compensating digital input delay in an intelligent electronic device is provided. A method is provided which provides for accurate SER data recording while facilitating the reduction of processing burden on the IED and optimization of system performance during the processing of SER data flow. An apparatus is further provided which generally includes a time delay element coupled to a sequential events recorder for compensating for delay in communication of a data signal such that the sequential events recorder records a compensated time for a select event based on the clock and the time delay. An apparatus is provided which includes an edge detection element for detecting either a rising or falling edge from the data signal.

Abstract: An RTD system includes multiple pluralities of RTDs and RTD bank assembly to which each plurality of RTDs are connected. Each RTD bank assembly includes a current source for the RTDs connected thereto, a multiplexer switching system for switching the current source successively between the RTDs, and a measurement function for measuring the voltage drop across the RTDs produced by the current source. The system includes a circuit for determining resistance of the RTD from the current applied thereto and the voltage drop there across. The system further includes a plurality of low pass filters associated, respectively, with each RTD, wherein the low pass filters are charged before the voltage measurement is made. The system includes a precharging arrangement where the low pass filter associated with the next RTD in a voltage sampling sequence is precharged, so that the delay between sampling of the voltage from the low pass filters associated with successive RTDs is significantly reduced.

Abstract: An architectural system for a protective relay used in an electric power system and responsive to analog signals from the electric power line includes a main circuit board which contains a processor for processing digital input signals to carry out specified protection functions. The system further includes an input signal board which includes current transformers (CTs) and potential transformers (PTs) for all three phases and low-pass filters associated therewith. Those components have correction factors associated therewith to correct errors produced by the components. The correction factors are stored on the boards having the components. The signals from the input signal board are applied to the main board for use by the processor, along with the correction factor(s) stored on the input signal board.