Abstract: A semiconductor memory device 40 includes an array of storage cells 130, addressable by row and column and specifically designed for testing. Row and column addresses are decoded to access a row and plural columns simultaneously. A test data bit to be written into the storage cells is replicated and stored into as many storage cells at once as there are columns simultaneously accessed. Upon readout for a comparison test, plural occurrences of the stored test data bit are compared with each other and with an expected data bit within parallel comparator circuitry 140 located within the memory device. A pass/fail signal (on lead 170) from the parallel comparator circuitry is transmitted to the memory device tester 30 for final defect analysis and correction. When a failure/defect is detected, information representing the address and the type of failure are stored in the memory device tester. A memory device test method also is described.