Abstract: A computing device may be configured to output a digital audio stream to an audio playback system for rendering as sound over speakers. The sound may be sampled. Based at least in part on a quality of the sampled sound, the data rate of the digital audio stream may be reduced by reducing a sampling rate and/or by reducing a number of bits per sample. A reduced sampling rate may be determined based on a computed maximum sampling rate of the audio playback system, and/or a reduced number of bits per sample may be determined based on a computed maximum number of bits per sample of the audio playback system. The maximum usable sampling rate and maximum usable number of bits per sample may be determined based on an upper usable frequency within a frequency spectrum of the sampled sound.

Abstract: A computing device may be configured to output a digital audio stream to an audio playback system for rendering as sound over speakers. The sound may be sampled. Based at least in part on a quality of the sampled sound, the data rate of the digital audio stream may be reduced by reducing a sampling rate and/or by reducing a number of bits per sample. A reduced sampling rate may be determined based on a computed maximum sampling rate of the audio playback system, and/or a reduced number of bits per sample may be determined based on a computed maximum number of bits per sample of the audio playback system. The maximum usable sampling rate and maximum usable number of bits per sample may be determined based on an upper usable frequency within a frequency spectrum of the sampled sound.

Abstract: A delay line circuit and method to delay digital data in a main memory is provided. The delay line circuit may comprise primary delay line cache, secondary delay line cache, and a cache controller to control communication of data between the secondary delay cache and the primary delay cache. The primary delay line cache may receive digital data to be delayed from a signal processor module, and secondary delay line cache may be connected to the primary delay line cache and the main memory to send data to and receive delayed data from the main memory. Data in the secondary delay line cache may be updated with data from the main memory or with data from the primary delay line cache. The invention extends to a machine-readable medium comprising a set of instructions for executing any of the methods described herein.

Abstract: A method and digital processor to process digital samples is provided. The processor may comprise a time domain processing engine to process a digital sample in the time domain, and a frequency domain processing engine to process a digital sample in the frequency domain. Shared memory is provided in the digital processor with which time domain and frequency domain processed samples are exchangeable. The time domain processing engine may processes data samples in a sample-by-sample manner and the frequency domain processing engine may processes data samples in a block-based manner. The processing engines may be integrated in a single DSP chip. In one embodiment, an interrupt generator is provided that generates an interrupt and an input buffer communicates an input data sample to the processor in response to the interrupt and the output buffer communicates an output data sample to the digital sample bus in response to the interrupt.

Abstract: A delay line circuit and method to delay digital data in a main memory is provided. The delay line circuit may comprise primary delay line cache, secondary delay line cache, and a cache controller to control communication of data between the secondary delay cache and the primary delay cache. The primary delay line cache may receive digital data to be delayed from a signal processor module, and secondary delay line cache may be connected to the primary delay line cache and the main memory to send data to and receive delayed data from the main memory. Data in the secondary delay line cache may be updated with data from the main memory or with data from the primary delay line cache. The invention extends to a machine-readable medium comprising a set of instructions for executing any of the methods described herein.

Abstract: A method for determining a position of a joystick in data communication with a processor and having an initial state that includes steps of varying the initial state in response to a signal from the processor; returning the joystick to the initial state after a duration of time, with the duration of time being dependent upon the position amongst a plurality of positions. A plurality of poll operations of the joystick are executed to sense the returning step. Each of the polling operations results in a data signal being transferred from the joystick indicating the state of the same, with consecutive poll operations being separated by a predetermined segment of time, defining a first interval and consecutive data signals operations being separated by a time period, defining a second interval. The second interval is increased to be greater than the first interval, the duration of time is measured by determining a number of data signals received by the processor between the varying step and the returning step.

Abstract: A system for debugging a processor includes logic circuits for communicating commands and data between a serial input/output port, a trace logic, and the processor. Some embodiments of the debugging system also include a parallel input/output port so that the logic circuits also communicate commands and data between the parallel input/output port, the trace logic, and the processor. The debug system includes a plurality of state machines that read the commands and data from the serial input/output ports. The commands are decoded by a decode logic. Some of the commands, such as commands for reading data from memory, utilize processor intervention and are transferred to the processor for execution. The state machines operate only on a single command at one time so that an active state machine does not accept additional commands until completion of the command that is currently executed.

Abstract: A communication system which includes more efficient packet conversion and routing for improved performance and simplified operation. The communication system includes one or more inputs for receiving packet data and one or more outputs for providing packet data. In one embodiment, the present invention comprises a "traffic circle" architecture for routing packet data and converting between different packet formats. In this embodiment, the system includes a data bus configured in a ring or circle. A plurality of port adapters or protocol processors are coupled to the ring data bus or communication circle. Each of the port adapters are configurable for converting between different types of communication packet formats. In the preferred embodiment, each of the port adapters are operable to convert between one or more communication packet formats to/from a generic packet format.

Abstract: A communication system which includes more efficient packet conversion and routing for improved performance and simplified operation. The present invention includes an improved method for converting data packets between a plurality of different packet formats using a pre-defined generic packet format for simplified conversions. In order to perform a packet conversion, the method first converts a data packet having a first packet format to a the pre-defined generic packet format. The method then converts the data packet having the predefined generic packet format to a desired second different packet format. The method is thus operable to convert a data packet having any of a plurality of possible packet format types to the pre-defined generic packet format, and to convert a data packet having the pre-defined generic packet format to a data packet having any of the plurality of possible packet format types.