Patents by Inventor Carl Wayne VINEYARD
Carl Wayne VINEYARD has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11841943Abstract: Various implementations described herein refer to a method for tracking abnormal incidents while monitoring activity of logic circuitry. The method may include detecting a tamper event related to the abnormal incidents and storing an attack signature related to the tamper event. The attack signature may be stored in non-volatile memory (NVM), such as, e.g., correlated electron random access memory (CeRAM).Type: GrantFiled: September 26, 2019Date of Patent: December 12, 2023Assignee: Arm LimitedInventors: Joshua Randall, Joel Thornton Irby, Carl Wayne Vineyard, Mudit Bhargava
-
Patent number: 11822705Abstract: An apparatus for masking power consumption associated with one or more operations of a logic circuitry of a processor. The apparatus comprises power-complementing circuitry configured to provide a second power consumption to directly power-complementing the power consumption associated with the one or more operations of the logic circuitry. The second power consumption complements the power consumption associated with the one or more operations of the logic circuitry. The apparatus further comprises header circuitry configured to enable a common node to vary in voltage corresponding to the one or more operations of the logic circuitry. The power-complementing circuitry and the header circuitry are each coupled to the logic circuitry at the common node.Type: GrantFiled: November 29, 2021Date of Patent: November 21, 2023Assignee: Arm LimitedInventors: Bal S. Sandhu, George McNeil Lattimore, Carl Wayne Vineyard
-
Patent number: 11550965Abstract: Analytics processing circuitry can include a data scavenger and a data analyzer coupled to receive the data from the data scavenger. The data scavenger collects data from at least one element of interest of a plurality of elements of interest of an IC. The data analyzer identifies patterns in the data from the data scavenger over a time frame or for a snapshot of time based on a predefined metric. The analytics processing circuitry can further include a moderator and a risk predictor. The risk predictor generates a risk assessment regarding whether the data collected by the data scavenger is indicative of normal behavior or abnormal behavior based at least on the output of the data analyzer and a behavioral model for the IC, which can be device and application specific. A threat response can be performed based on the risk assessment.Type: GrantFiled: April 22, 2020Date of Patent: January 10, 2023Assignee: ARM LIMITEDInventors: Subbayya Chowdary Yanamadala, Jeremy Patrick Dubeuf, Carl Wayne Vineyard, Matthias Lothar Boettcher, Hugo John Martin Vincent, Shidhartha Das
-
Patent number: 11361111Abstract: A computing device incorporating repetitive side channel attack (SCA) countermeasures can include a timer circuit and a capacitive delay circuit that notifies of a potential repetitive-based attack by sending an activity-detected signal that can be used to initiate an appropriate countermeasure response. Additionally, or independently, a computing device incorporating repetitive SCA countermeasures can include at least one storage unit that can store an incoming input signal, at least one comparator to compare the incoming input signal with another signal and indicate a match, and a counter that increments upon the match. When the counter reaches a specified limit, a limit-exceeded signal can be sent to notify of a potential repetitive-based attack and initiate an appropriate countermeasure response.Type: GrantFiled: July 9, 2018Date of Patent: June 14, 2022Assignee: ARM LIMITEDInventors: Carl Wayne Vineyard, Christopher Neal Hinds, Adeline-Fleur Fleming
-
Publication number: 20220083696Abstract: An apparatus for masking power consumption associated with one or more operations of a logic circuitry of a processor. The apparatus comprises power-complementing circuitry configured to provide a second power consumption to directly power-complementing the power consumption associated with the one or more operations of the logic circuitry. The second power consumption complements the power consumption associated with the one or more operations of the logic circuitry. The apparatus further comprises header circuitry configured to enable a common node to vary in voltage corresponding to the one or more operations of the logic circuitry. The power-complementing circuitry and the header circuitry are each coupled to the logic circuitry at the common node.Type: ApplicationFiled: November 29, 2021Publication date: March 17, 2022Inventors: Bal S. Sandhu, George McNeil Lattimore, Carl Wayne Vineyard
-
Patent number: 11232196Abstract: A computing device can include a comparator coupled to an I/O pin of the computing device; a storage unit coupled to the comparator; and a counter coupled to receive an output of the comparator, an output of the counter being coupled to a computation engine to provide a limit-exceeded signal to the computation engine, wherein the counter comprises a volatile counter and a nonvolatile storage, wherein the nonvolatile storage stores a bit for each top volatile count number of events identified by the volatile counter. The computing device can further include a backup power source coupled to the volatile counter; and readout circuitry and control logic coupled to the volatile counter and to the nonvolatile storage, the readout circuitry and control logic being configured to control operations of the volatile counter during an error event and determine a total number of events. The computing device can be a smart card.Type: GrantFiled: May 10, 2019Date of Patent: January 25, 2022Assignee: ARM LIMITEDInventors: Carl Wayne Vineyard, Christopher Neal Hinds, Subbayya Chowdary Yanamadala, Asaf Shen
-
Patent number: 11188682Abstract: An apparatus for masking power consumption associated with one or more operations of a logic circuitry of a processor. The apparatus comprises power-complementing circuitry configured to provide a second power consumption to directly power-complementing the power consumption associated with the one or more operations of the logic circuitry. The second power consumption complements the power consumption associated with the one or more operations of the logic circuitry. The apparatus further comprises header circuitry configured to enable a common node to vary in voltage corresponding to the one or more operations of the logic circuitry. The power-complementing circuitry and the header circuitry are each coupled to the logic circuitry at the common node.Type: GrantFiled: April 8, 2019Date of Patent: November 30, 2021Assignee: Arm LimitedInventors: Bal S. Sandhu, George McNeil Lattimore, Carl Wayne Vineyard
-
Publication number: 20210334415Abstract: Analytics processing circuitry can include a data scavenger and a data analyzer coupled to receive the data from the data scavenger. The data scavenger collects data from at least one element of interest of a plurality of elements of interest of an IC. The data analyzer identifies patterns in the data from the data scavenger over a time frame or for a snapshot of time based on a predefined metric. The analytics processing circuitry can further include a moderator and a risk predictor. The risk predictor generates a risk assessment regarding whether the data collected by the data scavenger is indicative of normal behavior or abnormal behavior based at least on the output of the data analyzer and a behavioral model for the IC, which can be device and application specific. A threat response can be performed based on the risk assessment.Type: ApplicationFiled: April 22, 2020Publication date: October 28, 2021Inventors: Subbayya Chowdary YANAMADALA, Jeremy Patrick DUBEUF, Carl Wayne VINEYARD, Matthias Lothar BOETTCHER, Hugo John Martin VINCENT, Shidhartha DAS
-
Publication number: 20210334373Abstract: A moderator system that can receive outputs of various stages of the security analytic framework and can receive input from external sources to provide information about emerging styles of attacks. One or more models/behavioral profiles can be curated by the moderator system, and the moderator system can provide updates to components of the security analytics framework.Type: ApplicationFiled: April 22, 2020Publication date: October 28, 2021Inventors: Subbayya Chowdary YANAMADALA, Jeremy Patrick DUBEUF, Carl Wayne VINEYARD, Matthias Lothar BOETTCHER, Hugo John Martin VINCENT, Shidhartha DAS
-
Patent number: 10997322Abstract: An apparatus is provided to enable power supply input to be isolated from power supply output. Power is received from a first power signal at a first of a plurality of charge stores. A second power signal is output from a second of the plurality of charge stores. The second power signal is isolated from the first power supply. The first charge store can be charged from the power input whilst isolated from the power output. The second charge store can be discharged to the power output, while isolated from the power input.Type: GrantFiled: May 1, 2018Date of Patent: May 4, 2021Assignee: Arm LimitedInventors: Adeline-Fleur Fleming, Carl Wayne Vineyard, George Mcneil Lattimore, Christopher Neal Hinds, Robert John Harrison, Mikael Rien, Abdellah Bakhali, Robert Christiaan Schouten, Jean-Charles Bolinhas
-
Publication number: 20210097173Abstract: Various implementations described herein refer to a method for tracking abnormal incidents while monitoring activity of logic circuitry. The method may include detecting a tamper event related to the abnormal incidents and storing an attack signature related to the tamper event. The attack signature may be stored in non-volatile memory (NVM), such as, e.g., correlated electron random access memory (CeRAM).Type: ApplicationFiled: September 26, 2019Publication date: April 1, 2021Inventors: Joshua Randall, Joel Thornton Irby, Carl Wayne Vineyard, Mudit Bhargava
-
Patent number: 10924261Abstract: An apparatus includes a power input, a power output, and a plurality of independent powering units each comprising at least one charge store. Each of the plurality of powering units is capable of receiving power from the power input while isolating the power output, and each of the plurality of powering units is capable of outputting power to the power output while isolating the power input.Type: GrantFiled: May 22, 2017Date of Patent: February 16, 2021Assignee: ARM LimitedInventors: Robert John Harrison, Mikael Rien, Carl Wayne Vineyard, George Mcneil Lattimore, Christopher Neal Hinds, Adeline-Fleur Fleming
-
Publication number: 20200012822Abstract: A computing device incorporating repetitive side channel attack (SCA) countermeasures can include a timer circuit and a capacitive delay circuit that notifies of a potential repetitive-based attack by sending an activity-detected signal that can be used to initiate an appropriate countermeasure response. Additionally, or independently, a computing device incorporating repetitive SCA countermeasures can include at least one storage unit that can store an incoming input signal, at least one comparator to compare the incoming input signal with another signal and indicate a match, and a counter that increments upon the match. When the counter reaches a specified limit, a limit-exceeded signal can be sent to notify of a potential repetitive-based attack and initiate an appropriate countermeasure response.Type: ApplicationFiled: July 9, 2018Publication date: January 9, 2020Inventors: Carl Wayne VINEYARD, Christopher Neal HINDS, Adeline-Fleur FLEMING
-
Publication number: 20200012783Abstract: A computing device can include a comparator coupled to an I/O pin of the computing device; a storage unit coupled to the comparator; and a counter coupled to receive an output of the comparator, an output of the counter being coupled to a computation engine to provide a limit-exceeded signal to the computation engine, wherein the counter comprises a volatile counter and a nonvolatile storage, wherein the nonvolatile storage stores a bit for each top volatile count number of events identified by the volatile counter. The computing device can further include a backup power source coupled to the volatile counter; and readout circuitry and control logic coupled to the volatile counter and to the nonvolatile storage, the readout circuitry and control logic being configured to control operations of the volatile counter during an error event and determine a total number of events. The computing device can be a smart card.Type: ApplicationFiled: May 10, 2019Publication date: January 9, 2020Inventors: Carl Wayne VINEYARD, Christopher Neal HINDS, Subbayya Chowdary YANAMADALA, Asaf SHEN
-
Publication number: 20190236315Abstract: An apparatus for masking power consumption associated with one or more operations of a logic circuitry of a processor. The apparatus comprises power-complementing circuitry configured to provide a second power consumption to directly power-complementing the power consumption associated with the one or more operations of the logic circuitry. The second power consumption complements the power consumption associated with the one or more operations of the logic circuitry. The apparatus further comprises header circuitry configured to enable a common node to vary in voltage corresponding to the one or more operations of the logic circuitry. The power-complementing circuitry and the header circuitry are each coupled to the logic circuitry at the common node.Type: ApplicationFiled: April 8, 2019Publication date: August 1, 2019Inventors: Bal S. Sandhu, George McNeil Lattimore, Carl Wayne Vineyard
-
Patent number: 10255462Abstract: An apparatus for obfuscating power consumption associated with one or more operations of a logic circuitry of a processor. The apparatus comprises counterbalance circuitry configured to provide a second power consumption to directly counterbalance the power consumption associated with the one or more operations of the logic circuitry. The second power consumption varies inversely with the power consumption associated with the one or more operations of the logic circuitry. The apparatus further comprises header circuitry configured to enable a common node to vary in voltage corresponding to the one or more operations of the logic circuitry. The counterbalance circuitry and the header circuitry are each coupled to the logic circuitry at the common node.Type: GrantFiled: June 17, 2016Date of Patent: April 9, 2019Assignee: ARM LimitedInventors: Bal S. Sandhu, George McNeil Lattimore, Carl Wayne Vineyard
-
Publication number: 20180337767Abstract: Power is received from a first power signal a first of a plurality of charge stores. A second power signal is output from a second of the plurality of charge stores. The second power signal is isolated from the first power supply.Type: ApplicationFiled: May 22, 2017Publication date: November 22, 2018Inventors: Robert John HARRISON, Mikael RIEN, Carl Wayne VINEYARD, George McNeil LATTIMORE, Christopher Neal HINDS, Adeline-Fleur FLEMING
-
Publication number: 20180336372Abstract: Power is received from a first power signal at a first of a plurality of charge stores. A second power signal is output from a second of the plurality of charge stores. The second power signal is isolated from the first power supply.Type: ApplicationFiled: May 1, 2018Publication date: November 22, 2018Inventors: Adeline-Fleur FLEMING, Carl Wayne VINEYARD, George McNeil LATTIMORE, Christopher Neal HINDS, Robert John HARRISON, Mikael RIEN, Abdellah BAKHALI, Robert Christiaan SCHOUTEN, Jean-Charles BOLINHAS
-
Publication number: 20170364710Abstract: An apparatus for obfuscating power consumption associated with one or more operations of a logic circuitry of a processor. The apparatus comprises counterbalance circuitry configured to provide a second power consumption to directly counterbalance the power consumption associated with the one or more operations of the logic circuitry. The second power consumption varies inversely with the power consumption associated with the one or more operations of the logic circuitry. The apparatus further comprises header circuitry configured to enable a common node to vary in voltage corresponding to the one or more operations of the logic circuitry. The counterbalance circuitry and the header circuitry are each coupled to the logic circuitry at the common node.Type: ApplicationFiled: June 17, 2016Publication date: December 21, 2017Inventors: Bal S. Sandhu, George McNeil Lattimore, Carl Wayne Vineyard
-
Patent number: 9454313Abstract: A data processing system includes a memory controller which dynamically selects from a plurality of candidate management algorithms a selected management algorithm to be used for managing memory access conflicts. The memory management algorithms may include various versions of speculative memory access issue and/or memory access issue using memory locks. The dynamic selection is performed on the basis of detected state parameters of the system. These detected state parameters may include conflict level indicators, such as memory access conflict counters tracked on one or more of a global, per-process, per-region or per-thread basis.Type: GrantFiled: June 10, 2014Date of Patent: September 27, 2016Assignee: ARM LimitedInventors: Christopher Neal Hinds, Steven D. Krueger, Carl Wayne Vineyard