Patents by Inventor Carl Werner

Carl Werner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040208257
    Abstract: A technique for utilizing spare bandwidth resulting from the use of a transition-limiting code in a multi-level signaling system is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for utilizing spare bandwidth resulting from the use of a transition-limiting code in a multi-level signaling system, wherein the transition-limiting code has a characteristic such that at least one signal level is periodically unused. The method comprises utilizing the at least one periodically unused signal level in a codeword that has been encoded using the transition-limiting code so as to represent additional information in the multi-level signaling system.
    Type: Application
    Filed: May 20, 2004
    Publication date: October 21, 2004
    Inventors: Anthony Bessios, William Stonecypher, Carl Werner, Jared Zerbe
  • Publication number: 20040161068
    Abstract: A circuit, apparatus and method for maximizing system margins by adjusting a duty-cycle of a clock signal in a receive circuit to whatever duty-cycle is optimal for the particular incoming serial data, rather than the typical 50% duty-cycle, is provided in embodiments of the present invention. A receive circuit, including duty-cycle-correction logic, is included in a double-data rate communication apparatus having a transmit circuit transmitting serial data having duty-cycle distortion. A receive circuit includes a first and second sampler to obtain data and edge values of an incoming serial data responsive to a data and edge clock, respectively. A duty-cycle-correction logic generates a duty-cycle-correction signal to a duty-cycle clock integrator that adjusts the edge clock signals while maintaining quadrature to the data clocks. In an embodiment of the present invention, a duty-cycle-correction logic includes an evaluator circuit to generate an up or down signal responsive to the data and/or edge values.
    Type: Application
    Filed: September 26, 2003
    Publication date: August 19, 2004
    Inventors: Jared Zerbe, Mark Horowitz, Carl Werner
  • Patent number: 6772351
    Abstract: A current controller for a multi-level current mode driver. The current controller includes a multi-level voltage reference and at least one source calibration signal. A comparator is coupled by a coupling network to the multi-level voltage reference and the at least one source calibration signal. A selected voltage is applied from the multi-level voltage reference and a selected source calibration signal is applied from the at least one source calibration signal to the comparator.
    Type: Grant
    Filed: September 5, 2000
    Date of Patent: August 3, 2004
    Assignee: Rambus, Inc.
    Inventors: Carl Werner, Mark Horowitz, Pak Chau, Scott Best, Stefanos Sidiropoulos
  • Publication number: 20040109510
    Abstract: A technique for utilizing spare bandwidth resulting from the use of a transition-limiting code in a multi-level signaling system is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for utilizing spare bandwidth resulting from the use of a transition-limiting code in a multi-level signaling system, wherein the transition-limiting code has a characteristic wherein a signal level is periodically unused. Such a method may comprise modifying the transition-limiting code such that the periodically unused signal level is used to represent additional information.
    Type: Application
    Filed: September 23, 2003
    Publication date: June 10, 2004
    Inventors: Anthony Bessios, William Stonecypher, Jared Zerbe, Carl Werner
  • Publication number: 20020091948
    Abstract: A method for improving resolution of a current mode driver. The current mode driver is operable to provide an output that falls within a predetermined range. An embodiment of the method includes sensing a condition, such as a process condition, a voltage condition and a temperature condition. A full scale current of a digital-to-analog converter is adjusted in accordance with the condition. A current control signal is set based on an output of the digital-to-analog converter. The sensing step may include measuring a process, voltage or temperature sensitive DC parameter. Alternatively, the sensing step may include sensing a process, voltage or temperature sensitive AC parameter.
    Type: Application
    Filed: December 20, 2000
    Publication date: July 11, 2002
    Inventors: Carl Werner, Pak Shing Chau
  • Publication number: 20020075968
    Abstract: A system and method are shown for generation of at least one reference voltage level in a bus system. A reference voltage generator on a current driver includes at least one reference voltage level, at least one control signal, and an active device. The active device is coupled to the at least one control signal, such as a current control signal, and a selected reference voltage of the at least one reference voltage level. The active device is arranged to shift the at least one reference voltage level based on the at least one current control signal such as an equalization signal, a crosstalk signal, or the combination thereof, employed on the current driver.
    Type: Application
    Filed: September 27, 2001
    Publication date: June 20, 2002
    Inventors: Jared Zerbe, Carl Werner