Patents by Inventor Carl Zeitler

Carl Zeitler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040260832
    Abstract: Improved techniques are provided for reducing latency in inter-cluster communications within computer systems having a plurality of multi-processor clusters. The local nodes of each cluster include a plurality of processors and an interconnection controller. Intra-cluster links are formed between the local nodes, including the interconnection controller, within a cluster. Inter-cluster links are formed between interconnection controllers of different clusters. Intra-cluster packets may be encapsulated as inter-cluster packets and stored in a transmission buffer pending transmission on an inter-cluster link. When the transmission buffer is empty, a control character is transmitted on an inter-cluster link. The control character is not stored in the transmission buffer or in a reception buffer, but instead is dropped. Clock data may be embedded in symbols sent on each bit lane of the inter-cluster links, including the symbol(s) of the control character.
    Type: Application
    Filed: June 23, 2003
    Publication date: December 23, 2004
    Applicant: Newisys, Inc., A Delaware corporation
    Inventors: Rajesh Kota, Shashank Nemawarkar, Guru Prasadh, Carl Zeitler, David B. Glasco
  • Publication number: 20040255002
    Abstract: According to the present invention, methods and apparatus are provided for increasing the efficiency and effectiveness of communications between multiprocessor clusters. Mechanisms for improving the accuracy of information available to an interconnection controller are implemented in order to allow the interconnection controller to increase reliability and reduce latency in a multiple cluster system. Protocol extensions and link layer extensions are provided with packets to convey information between interconnection controllers of separate multiprocessor clusters.
    Type: Application
    Filed: June 12, 2003
    Publication date: December 16, 2004
    Applicant: Newisys, Inc., A Delaware corporation
    Inventors: Rajesh Kota, Shashank Newawarker, Guru Prasadh, Carl Zeitler, David B. Glasco
  • Publication number: 20040210693
    Abstract: A computer system is described having a plurality of processing nodes interconnected by a first point-to-point architecture, and a system memory including a plurality of portions each of which is associated with one of the processing nodes. Each processing node includes a processor, and a memory controller for controlling access to the associated portion of the system memory, and may contain a host bridge for facilitating communication with a plurality of I/O devices. The first point-to-point architecture is operable to facilitate first transactions between the processors and the system memory. The computer system further includes at least one I/O controller and a second point-to-point architecture independent of the first point-to-point architecture and interconnecting the I/O controller and the host bridges. The at least one I/O controller is operable to facilitate second transactions between the I/O devices and the system memory via the second point-to-point architecture.
    Type: Application
    Filed: April 15, 2003
    Publication date: October 21, 2004
    Applicant: Newisys, Inc.
    Inventors: Carl Zeitler, David B. Glasco, Rajesh Kota, Guru Prasadh, Richard R. Oehler, David S. Edrich
  • Publication number: 20040153507
    Abstract: Methods and apparatus are provided for improving the distribution of system management signals within a computer system complex. Mechanisms are provided for transmission both within a box and between computer system boxes. Local routing tables and general routing tables allow the distribution of system management signals precisely to resources associated with particular partitions. Signals are sequenced to put resources associated with one or more boxes in the appropriate states. The distribution of signals between boxes in the computer system complex can be accomplished with the use of a dedicated wire.
    Type: Application
    Filed: January 30, 2003
    Publication date: August 5, 2004
    Applicant: Newisys, Inc. A Delaware corporation
    Inventors: Carl Zeitler, David Brian Glasco, Les Record, Richard R. Oehler, William G. Kulpa, Guru Prasadh, Rajesh Kota
  • Publication number: 20040098475
    Abstract: Methods and apparatus are provided for improving the distribution of system management signals within a computer system complex. Mechanisms are provided for transmission both within a box and between computer system boxes. Local routing tables and general routing tables allow the distribution of system management signals precisely to resources associated with particular partitions. Signals are sequenced to put resources associated with one or more boxes in the appropriate states. The distribution of signals between boxes in the computer system complex can be accomplished without the use of a dedicated wire.
    Type: Application
    Filed: November 19, 2002
    Publication date: May 20, 2004
    Applicant: Newisys, Inc., A Delaware Corporation
    Inventors: Carl Zeitler, David Brian Glasco, Les Record, Richard R. Oehler, William G. Kulpa, Guru Prasadh, Rajesh Kota
  • Publication number: 20040015628
    Abstract: An interconnection controller for use in a computer system having a plurality of processor clusters is described. Each cluster includes a plurality of local nodes and an instance of the interconnection controller. The interconnection controller is operable to transmit locally generated interrupts to others of the clusters, and remotely generated interrupts to the local nodes. The interconnection controller is further operable to aggregate locally generated interrupt responses for transmission to a first remote cluster from which a first interrupt corresponding to the locally generated responses was generated. The interconnection controller is also operable to aggregate remotely generated responses for transmission to a first local node from which a second interrupt corresponding to the remotely generated responses was generated. A computer system employing such an interconnection controller is also described.
    Type: Application
    Filed: July 19, 2002
    Publication date: January 22, 2004
    Applicant: Newisys, Inc.
    Inventors: David Brian Glasco, Carl Zeitler
  • Publication number: 20040003303
    Abstract: According to the present invention, methods and apparatus are provided for static and dynamic power management of computer systems. A power authority manages power usage levels in computer systems by monitoring power consumption levels and providing power consumption information to the various systems. In one example, the power authority updates power tables to vary aggregate power consumption levels.
    Type: Application
    Filed: July 1, 2002
    Publication date: January 1, 2004
    Applicant: Newisys, Inc.
    Inventors: Richard R. Oehler, Carl Zeitler, Richard O. Simpson
  • Publication number: 20030233388
    Abstract: A multi-processor computer system is described in which address mapping, routing, and transaction identification mechanisms are provided which enable the interconnection of a plurality of multi-processor clusters, wherein the number of processors interconnected exceeds limited address, node identification, and transaction tag spaces associated with each of the individual clusters.
    Type: Application
    Filed: May 28, 2002
    Publication date: December 18, 2003
    Applicant: NEWISYS, Inc. A Delaware corporation
    Inventors: David Brian Glasco, Carl Zeitler, Rajesh Kota, Guru Prasadh, Richard R. Oehler
  • Publication number: 20030225909
    Abstract: A multi-processor computer system is described in which address mapping, routing, and transaction identification mechanisms are provided which enable the interconnection of a plurality of multi-processor clusters, wherein the number of processors interconnected exceeds limited address, node identification, and transaction tag spaces associated with each of the individual clusters.
    Type: Application
    Filed: May 28, 2002
    Publication date: December 4, 2003
    Applicants: NEWISYS, Inc., A Delaware corporation
    Inventors: David Brian Glasco, Carl Zeitler, Rajesh Kota, Guru Prasadh, Richard R. Oehler
  • Publication number: 20030225938
    Abstract: A multi-processor computer system is described in which address mapping, routing, and transaction identification mechanisms are provided which enable the interconnection of a plurality of multi-processor clusters, wherein the number of processors interconnected exceeds limited address, node identification, and transaction tag spaces associated with each of the individual clusters.
    Type: Application
    Filed: May 28, 2002
    Publication date: December 4, 2003
    Applicant: Newisys, Inc., A Delaware corporation
    Inventors: David Brian Glasco, Carl Zeitler, Rajesh Kota, Guru Prasadh, Richard R. Oehler
  • Patent number: 5444854
    Abstract: A data processing system including a processor that issues communications commands on a first communications channel and a peripheral device that is connected to the first communications channel and to a second communications channel that operates asynchronously relative to the first communications channel. The peripheral device performs communications operations specified from the commands from the processor and further responds to communications over the second communications channel. The peripheral device includes a controller that provides a status word to the processor in response to the command issued to the peripheral device. The status word indicates the status condition of the peripheral device at the time when the peripheral device initiates the operation specified by the issued command.
    Type: Grant
    Filed: March 6, 1992
    Date of Patent: August 22, 1995
    Assignee: International Business Machines Corporation
    Inventors: Joseph R. Mathis, Richard R. Oehler, Carl Zeitler, Jr.
  • Patent number: 4995056
    Abstract: In a communications system, a sending system and a receiving system have multiple data buffers. In response to an inquiry from the sending system, the receiving system transmits information which indicates the size and number of data buffers available in the receiving system. The sending system then begins transmitting data frames, which are placed into the buffers of the receiving system. When the receiving system removes all of the data from a buffer, therefore freeing it to accept additional data, it sends a signal to the sending system indicating this fact. The sending system counts such signals, and ensures that the number of transmitted data frames does not exceed the number of frames which have been removed from the receiver's buffers by more than the number of buffers which the receiver has.
    Type: Grant
    Filed: January 13, 1989
    Date of Patent: February 19, 1991
    Assignee: International Business Machines Corporation
    Inventors: Richard G. Fogg, Jr., Joseph R. Mathis, Carl Zeitler, Jr.
  • Patent number: 4497022
    Abstract: A channel for a data processing system is provided with a time of day clock that is synchronized with the time of day clock of the associated central processor. Both the central processor and the channel processor record times of particular events, and the channel uses these times to calculate two times called Function Pending and Function Active. Both times begin when the central processor executes an instruction to begin an I/O operation. Function Pending ends when the channel has made successful initial selection. This time shows delays by the channel processor in scheduling the channel control unit, and device resources for I/O operations. Function Active ends at Channel End. A new instruction, Set Channel Monitor, enables or disables these measurements. An information block for each subchannel defines one of several measurement modes for a subchannel or disables the subchannel from measurement.
    Type: Grant
    Filed: October 19, 1982
    Date of Patent: January 29, 1985
    Assignee: International Business Machines Corporation
    Inventors: Roger L. Cormier, Robert J. Dugan, Richard R. Guyette, Ronald L. Hankison, Ming C. Hao, Arthur L. Levin, George A. McClain, Paul J. Wanish, Carl Zeitler, Jr.
  • Patent number: 4455605
    Abstract: Multiprocessing systems having changeable CPU configurations generate unique changeable identifications (ID's). These are presented by I/O channels over various I/O connection paths, in association with special path defining commands and function data. Related path state indications are stored peripherally in path map tables and define path group associations for sustaining path-independent I/O operations. When a device is reserved via one path in a path group the reserve affiliation is extended automatically (in the path tables ) to each path in the group, thereby rendering each path accessible in a reserved mode. The path defining commands are used for adding paths to, resigning paths from and disbanding groups. Special sensing commands are used for sensing path reservation and grouping states. When a command for adding or resigning a path is presented to a reserved device via one path in a group the reserve is automatically realigned to the enlarged or reduced group.
    Type: Grant
    Filed: July 23, 1981
    Date of Patent: June 19, 1984
    Assignee: International Business Machines Corporation
    Inventors: Roger L. Cormier, Robert J. Dugan, Richard R. Guyette, Paul J. Wanish, Carl Zeitler, Jr.
  • Patent number: 4445176
    Abstract: Secondary storage subsystems exchange messages and data with host data processing systems and also forward messages between host systems. Host systems thereby communicate with each other in addition to having access to data in subsystem storage. Access to subsystem storage is initiated by a "request" sent from a host to the subsystem. Each request is a message containing an array of one or more commands, each command specifying a transfer of data or a control function to be performed by the subsystem. A subsystem may process more than one request at a time. It also may process the commands in a request in an arbitrary sequence suited to the availability of subsystem resources and data links to host systems. After all commands in a request have been processed the subsystem transmits an associated "completion" message to the host system which originated the request. The completion message indicates the status of completion or abnormal termination of each command in the associated request.
    Type: Grant
    Filed: December 28, 1979
    Date of Patent: April 24, 1984
    Assignee: International Business Machines Corporation
    Inventors: John L. Burk, Roger L. Cormier, Michael H. Hartung, Ray A. Larner, Donald J. Lucas, Kenneth R. Lynch, Brian B. Moore, Howard L. Page, David H. Wansor, Carl Zeitler, Jr.
  • Patent number: 4271468
    Abstract: The disclosure relates to multiprocessor handling of plural queues of pending I/O interrupt requests (I/O IRs) in a main storage (MS) shared by plural central processors (CPs). An input/output processor (IOP) inserts I/O IR entries onto the queues in accordance with the type of interrupt. The entries in the queues are only removed by the CPs, after their selection by a system controller (SC) for execution of an interruption handling program.An I/O interrupt pending register in I/O interrupt controller circuits in the SC is used in selecting CPs to handle the I/O IRs on the queues. The bit positions in the pending register are respectively assigned to the I/O IR queues in MS, and the order of the bit positions determines the priority among the queues for CP handling. An I/O IR command from the IOP to the SC sets a corresponding queue bit position in the pending register and controls the addition of an entry on the corresponding queue in MS.
    Type: Grant
    Filed: November 6, 1979
    Date of Patent: June 2, 1981
    Assignee: International Business Machines Corp.
    Inventors: Neal T. Christensen, William C. Van Loo, Robert H. Werner, Joseph A. Wetzel, Carl Zeitler, Jr.