Abstract: A MOS capacitor comprises a semiconductor substrate, a first well region of a first conductivity type formed in the substrate, at least one doped region formed in the first well region, and an insulated gate layer insulatively disposed over a surface of the first well region. The at least one doped region and the insulated gate layer respectively form a first and a second electrode of the capacitor. The first well region is electrically connected to the at least one doped region to be at a same electrical potential of the first terminal of the capacitor.

Abstract: A MOS capacitor comprises a semiconductor substrate, a first well region of a first conductivity type formed in the substrate, at least one doped region formed in the first well region, and an insulated gate layer insulatively disposed over a surface of the first well region. The at least one doped region and the insulated gate layer respectively form a first and a second electrode of the capacitor. The first well region is electrically connected to the at least one doped region to be at a same electrical potential of the first terminal of the capacitor.

Abstract: An output circuit for an integrated circuit, includes a first transistor and a second transistor connected in series between a first external voltage and a second external voltage external to the integrated circuit, respectively through first and second electrical connecting paths. The first transistor is for carrying an output line of the integrated circuit to the first external voltage, while the second transistor is for carrying the external line of the integrated circuit to the second external voltage. The second transistor is formed inside a first well of a first conductivity type contained inside a second well of a second conductivity type formed in a substrate of the first conductivity type. The second well of the second conductivity type is connected to the first external voltage through a third electrical connecting path distinct from the first electrical connecting path.

Abstract: A boosting circuit supplied by a first voltage level and a second voltage level, and having an output line capable of taking a third voltage level, the circuit having at least two distinct circuits for generating the third voltage level, the at least two circuits selectively activatable for generating the third voltage level and selectively coupleable to the output line.

Abstract: Switching circuit comprising a reference voltage, an input voltage, suitable to assume alternatively a negative value or a value equal to said reference voltage, an output node, suitable to assume selectively three possible voltage values equal to a supply voltage, to the reference voltage, to the input voltage or, alternatively, to be kept floating, in response to a first, a second, a third, a fourth, a fifth, a sixth control logic signal, switching between the supply voltage and the reference voltage.

Abstract: A switching circuit comprising a supply voltage, a reference voltage, a line suitable to carry a negative voltage, an input for a control signal, suitable to supply to a first output node and to a second output node two voltages respectively equal to supply voltage and to line voltage or, alternatively, to line voltage and to supply voltage, in response to the control signal.

Abstract: A circuit for generating biasing signals in reading of a redundant UPROM cell incorporating at least one memory element of the EPROM or flash type and having a control terminal and a conduction terminal to be biased, as well as MOS transistors connecting the memory element with a reference low supply voltage comprises a voltage booster for generating a first voltage output signal to be applied to the control terminal of the memory element and a limitation network for the voltage signal connected to the output of the voltage booster. There is also provided a circuit portion for generating a second voltage output signal to be applied to the control terminal of one of the above mentioned transistors. This circuit portion comprises a timing section interlocked with the voltage booster of a section generating the second voltage signal.

Abstract: An address transition detection circuit having a number of cells supplied with respective address signals and outputs connected in a wired NOR configuration to generate a pulse signal on detecting transitions of their respective address signals. The pulse signal is supplied to a source stage for generating an address transition signal having a first and second switching edge on receiving the pulse signal. The source stage has a monostable stage for generating an end-of-transition signal with a predetermined delay following reception of the pulse signal; and an output stage connected to the cells and to the monostable stage, which generates the first switching edge of the address transition signal on receiving the pulse signal, and the second switching edge on receiving the end-of-transition signal. The monostable stage presents a compensating structure for maintaining the delay in the switching of the end-of-transition signal despite variations in temperature and supply voltage.

Abstract: A voltage booster comprising a charge pump for generating a boost voltage over a boost line. The booster comprises a comparator which is supplied by a voltage divider with a voltage proportional to the boost voltage, and by a reference source with a low reference voltage, and which, depending on the outcome of the comparison, enables or disables the charge pump. A voltage limiter is connected between the boost line and ground; and a acceleration circuit accelerates the voltage increase on the acceleration line following low-power operation in which the paths toward ground are interrupted for reducing consumption.

Abstract: A circuit for generating data load pulses of variable length as required includes a source for supplying a short load signal, and a delay element for generating longer pulses as of the short load signal. A static operating mode is provided wherein a load pulse is generated and maintained throughout static operation or as long as critical conditions (standby state, low voltage) persist. An extended pulse is always generated on exiting static operating mode; and the delay element may be disabled by a command when extended timing is not required.

Abstract: A method for programming non-volatile row redundancy memory registers. Each register is associated with a respective pair of redundancy row and each one programmable to store in two subsets of a set of memory cells a pair of addresses of a respective pair of adjacent defective rows. Each memory register is supplied with row address signals and with a respective selection signal belonging to a set of column address signals.