Abstract: A full reset flyback regulator includes a power transformer having a primary winding and at least one secondary winding coupled to a load. A single control winding on a primary side of the power transformer is coupled through control circuitry to a gate electrode of a switching device that is connected to the primary winding. The voltage polarity on the control winding alternates so that if the switching device is "ON" a drive voltage is provided on its gate electrode and if the switching device is "OFF" a bias voltage is provided to the error amplifier control circuit. Each cycle of the regulator is initiated via a sync pulse which is provided from the high voltage flyback transformer of a display or monitor subsystem.

Abstract: A non-interfering power supply includes a free-running blocking oscillator power supply subsystem and a circuit arrangement that synchronizes the blocking oscillator power supply subsystem to operate at the horizontal operating frequency of a display subsystem. Synchronizing signals representative of the horizontal operating frequency of the display subsystem are generated and are used to activate the circuit arrangement that causes the blocking oscillator to change its mode of operation from free-running to a fully reset fixed frequency flyback converter. When activated, a switch in the circuit arrangement extends the off-time of a switching transistor in the blocking oscillator power supply control circuit. As a result, the oscillator is forced to run at an operating frequency lower than its free-running frequency.

Abstract: A protective circuit arrangement is provided for shutting down a power supply at the occurrence of a fault condition. The circuit arrangement allows current limiting in a switching transistor during a power on and/or power off cycle, but shuts down the power supply if current limiting occurs at any other time.

Abstract: A power line disturbance (PLD) detector circuit includes a digital counter which is driven by pulses provided by a clock in an associated data processing system. The PLD detector circuit includes a comparator amplifier for comparing primary AC power to a DC reference voltage on a cycle-by-cycle basis. The amplifier generates a reset pulse once during each AC cycle as long as the AC voltage exceeds the DC reference voltage. When a decoder circuit detects a count outside the range of counts attained by the digital counter between normally occurring reset pulses, the decoder circuit responds by generating a PLD signal. The PLD signal is provided both to the associated data processing system and to a Power On Reset circuit. The Power On Reset circuit is initialized by the PLD signal, permitting the circuit to respond consistently upon subsequent restoration of power.