Abstract: An integrated circuit includes a sub-system and a reference sub-system. The reference sub-system is substantially identical to the sub-system but is non-operating by default. The integrated circuit includes a test circuit that obtains a parameter value of the sub-system and a reference parameter from the reference sub-system. The integrated circuit detects deterioration of the sub-system based on the parameter value and the reference parameter. The integrated circuit deactivates the sub-system and activates the reference sub-system responsive to detecting deterioration of the sub-system.

Abstract: An integrated circuit includes a sub-system and a reference sub-system. The reference sub-system is substantially identical to the sub-system but is non-operating by default. The integrated circuit includes a test circuit that obtains a parameter value of the sub-system and a reference parameter from the reference sub-system. The integrated circuit detects deterioration of the sub-system based on the parameter value and the reference parameter. The integrated circuit deactivates the sub-system and activates the reference sub-system responsive to detecting deterioration of the sub-system.

Abstract: An electronic device includes an electronic component having terminals including a set of first terminals and a set of second terminals, a protective package embedding the electronic component, leads exposed from the protective package including a set of first leads and a set of second leads, for each first lead a first electrical connection inside the protection package between the first lead and a corresponding one of the first terminals, and for each second lead electrical connections inside the protective package each one between the second lead and a corresponding one of the second terminals. For each second lead the electronic component includes test structures, each being coupled between a corresponding one of the second terminals connected to the second lead and a corresponding test one of the first terminals connected to a test one of the first leads.

Abstract: A solar light concentration photovoltaic conversion system, uses a solar light collector to focus collected light onto a termination of at least one multi-fiber cable. A wavelength splitter is optically coupled to the other termination of the multi-fiber cable for producing light beams of different wavelengths, each illuminating the optical termination of one or more lambda-dedicated tap fibers or multi-fiber cables. From the wavelength splitter depart a number of lambda-dedicated groups of tap fibers adapted to convey the radiation to remotely arranged lambda-specific photovoltaic cells, configured for efficiently converting light energy of the specific wavelength spectrum carried along respective fiber or group of fibers into electrical energy. The lambda-specific photovoltaic cells are formed onto light spreading structures optically coupled to a respective tap fiber or multi-fiber cable, adapted to trap the injected light and convert it into electricity.

Abstract: An electronic device includes an electronic component having terminals including a set of first terminals and a set of second terminals, a protective package embedding the electronic component, leads exposed from the protective package including a set of first leads and a set of second leads, for each first lead a first electrical connection inside the protection package between the first lead and a corresponding one of the first terminals, and for each second lead electrical connections inside the protective package each one between the second lead and a corresponding one of the second terminals. For each second lead the electronic component includes test structures, each being coupled between a corresponding one of the second terminals connected to the second lead and a corresponding test one of the first terminals connected to a test one of the first leads.

Abstract: A flash NAND electronic memory device includes non-volatile cells having a high integration density and a relative programming method. The memory device is integrated on a semiconductor substrate and includes a matrix with word lines and bit lines organized in sectors of memory cells. The memory device is between the cells of the opposite word lines belonging to at least one of the sectors of the matrix. A lateral coating along the direction of the bit lines has at least one conductive layer with a contact terminal being selectively biased or left floating during each program, read or erase operation. Each cell belongs to a sector.

Abstract: An electronic memory device with a high density of non-volatile memory cells has a reduced capacitance cell-to-cell interference. The memory cells are integrated on a semiconductor substrate and are organized in a matrix of cells with word lines and bit lines connected to the cells. Each memory cell includes at least one floating gate transistor having a floating gate region projecting from the substrate, and a control gate region capacitively coupled to the floating gate region. Between the cells of opposite word lines, a lateral coating is provided that includes at least one conductive layer floating along the direction of the bit lines.

Abstract: A process for manufacturing a MOS device is described. The process comprising: providing a body of semiconductor material having a surface; forming a stack on the surface of the body, the stack including a first polysilicon region, an intermediate dielectric region arranged on top of the first polysilicon region, and a second polysilicon region arranged on top of the intermediate dielectric region; depositing a passivation layer on top of and laterally to the stack; and forming at least one electrical connection region in direct electrical contact with the first and second polysilicon regions, wherein the electrical connection region is formed laterally with respect to both the first and second polysilicon regions.

Abstract: A MOS device has: a semiconductor body defining a surface; a stack on top of the semiconductor body; and a passivation layer on top of the semiconductor body and covering the stack. The stack is formed by a first polysilicon region and by a second polysilicon region arranged on top of one another and separated by an intermediate dielectric region. An electrical connection region extends through the passivation layer as far as the surface of the semiconductor body laterally with respect to, and in contact with, the first and the second polysilicon regions so as to contact them electrically.

Abstract: An electronic memory device with a high density of non-volatile memory cells has a reduced capacitance cell-to-cell interference. The memory cells are integrated on a semiconductor substrate and are organized in a matrix of cells with word lines and bit lines connected to the cells. Each memory cell includes at least one floating gate transistor having a floating gate region projecting from the substrate, and a control gate region capacitively coupled to the floating gate region. Between the cells of opposite word lines, a lateral coating is provided that includes at least one conductive layer floating along the direction of the bit lines.

Abstract: A flash NAND electronic memory device includes non-volatile cells having a high integration density and a relative programming method. The memory device is integrated on a semiconductor substrate and includes a matrix with word lines and bit lines organized in sectors of memory cells. The memory device is between the cells of the opposite word lines belonging to at least one of the sectors of the matrix. A lateral coating along the direction of the bit lines has at least one conductive layer with a contact terminal being selectively biased or left floating during each program, read or erase operation. Each cell belongs to a sector.

Abstract: An MOS device has a stack and a passivation layer covering the stack. The stack is formed by a first polysilicon region and by a second polysilicon region arranged on top of one another and separated by an intermediate dielectric region. An electrical connection region, formed by a column structure substantially free of steps, extends through the passivation layer, the second polysilicon region and the intermediate dielectric region, and terminates in contact with the first polysilicon region so as to electrically contacting the first polysilicon region and the second polysilicon region. Fabrication of the electrical connection region requires just one mask.

Abstract: A MOS device has: a semiconductor body defining a surface; a stack on top of the semiconductor body; and a passivation layer on top of the semiconductor body and covering the stack. The stack is formed by a first polysilicon region and by a second polysilicon region arranged on top of one another and separated by an intermediate dielectric region. An electrical connection region extends through the passivation layer as far as the surface of the semiconductor body laterally with respect to, and in contact with, the first and the second polysilicon regions so as to contact them electrically.

Abstract: An MOS device has a stack and a passivation layer covering the stack. The stack is formed by a first polysilicon region and by a second polysilicon region arranged on top of one another and separated by an intermediate dielectric region. An electrical connection region, formed by a column structure substantially free of steps, extends through the passivation layer, the second polysilicon region and the intermediate dielectric region, and terminates in contact with the first polysilicon region so as to electrically contacting the first polysilicon region and the second polysilicon region. Fabrication of the electrical connection region requires just one mask.