Abstract: A method and apparatus are provided for decoding a plurality of codewords from a received binary bitstream. A first decoding stage processes each of the codewords with a first iterative decoding algorithm based on forward error-correction information of the codewords. A second decoding stage processes selected ones of the codewords with a second iterative decoding algorithm, which is based on forward error-correction information in the selected ones of the codewords. Each codeword selected for the second decoding stage is selected in response to an exit from the decoding of that codeword without the production of a decoded codeword. The second iterative decoding algorithm is configured to enable a greater number of iterations of decoding per codeword than the first iterative decoding algorithm.

Abstract: An apparatus, comprising: circuitry configured, in response to receipt of input data, to transmit a stream of symbols of a constellation to a modulator for modulation onto a carrier wherein a frequency of occurrence of symbols in the stream is dependent upon a probability-amplitude distribution for symbols of the constellation, wherein the probability-amplitude distribution has a kurtosis less than a target value and a shape of the probability-amplitude distribution causes low-amplitude symbols to occur more frequently on average in the stream than high-amplitude symbols.

Abstract: An apparatus, comprising: circuitry configured, in response to receipt of input data, to transmit a stream of symbols of a constellation to a modulator for modulation onto a carrier wherein a frequency of occurrence of symbols in the stream is dependent upon a probability-amplitude distribution for symbols of the constellation, wherein the probability-amplitude distribution has a kurtosis less than a target value and a shape of the probability-amplitude distribution causes low-amplitude symbols to occur more frequently on average in the stream than high-amplitude symbols.

Abstract: An apparatus includes a digital signal processor to perform perturbation-based optical nonlinearity compensation of optical data signals of a communication stream. The digital signal processor includes first digital circuits to calculate multiplicative factors for corrections to the optical data signals from products of values of the optical data signals at a reduced set of times. The reduced set is a down-sampling of the sequence of consecutive symbol times of the communication stream. The digital signal processor also includes second digital circuits to calculate the multiplicative factors for corrections to the optical data signals at the consecutive symbol times by interpolating the multiplicative factors evaluated at the reduced set of times.

Abstract: A coherent optical receiver in which the channel equalizer and the clock-recovery circuit are connected in a nested-loop configuration, wherein the channel estimate generated by the equalizer is used to adjust the phase of the clock signal generated by the clock-recovery circuit. The channel equalizer can be implemented using a bank of time-domain or frequency-domain FIR filters. In an example embodiment, the clock-recovery circuit is configured to track the phase rotation corresponding to the equalized signals in a frequency-dependent manner; track the phase rotation in the channel equalizer either in a frequency-dependent manner or based on the mean signal delay therein; and adjust the phase of the clock signal based on an effective difference between these two phase rotations. The clock-recovery circuit enhances the clock tone by applying a Fourier transform to the squared absolute values of the equalized signals outputted by the channel equalizer.

Abstract: A coherent optical receiver in which the channel equalizer and the clock-recovery circuit are connected in a nested-loop configuration, wherein the channel estimate generated by the equalizer is used to adjust the phase of the clock signal generated by the clock-recovery circuit. The channel equalizer can be implemented using a bank of time-domain or frequency-domain FIR filters. In an example embodiment, the clock-recovery circuit is configured to track the phase rotation corresponding to the equalized signals in a frequency-dependent manner; track the phase rotation in the channel equalizer either in a frequency-dependent manner or based on the mean signal delay therein; and adjust the phase of the clock signal based on an effective difference between these two phase rotations. The clock-recovery circuit enhances the clock tone by applying a Fourier transform to the squared absolute values of the equalized signals outputted by the channel equalizer.

Abstract: The application is related to a forward error correction mechanism in an optical coherent communication system (CS) comprising a FEC encoder (FE) and a FEC decoder (FD) on the basis of a low density parity check, LDPC, code. The FEC encoder encodes blocks of client bits into codewords by adding parity bits calculated by applying a FEC code to the client bits. Besides, the FEC decoder decodes each codeword by applying thereto an iterative message-passing algorithm, each iteration of the message-passing algorithm comprising evaluating a parity-check matrix defining the FEC code. At the FEC encoder, the coding rate of the FEC code may be varied by varying the number of client/information bits per codeword and/or the number of parity bits per codeword. At the FEC decoder, the parity-check matrix is evaluated column by column at each iteration of the message-passing algorithm. The decoder may be a belief propagation decoder.

Abstract: It is disclosed an optical coherent receiver for an optical communication network. The optical coherent receiver is configured to receive a modulated optical signal and to process it for generating an in-phase component and a quadrature component. The optical coherent receiver comprises a power adjuster in turn comprising a multiplying unit and a retroactively connected digital circuit. The multiplying unit is configured to multiply the in-phase and quadrature components by in-phase and quadrature gains, respectively, thereby providing power-adjusted in-phase and quadrature components. The digital circuit is configured to compute: a common gain indicative of a sum of the powers of the power-adjusted in-phase and quadrature components; a differential gain indicative of a difference between the powers of the power-adjusted in-phase and quadrature components; and the in-phase and quadrature gains as a product and a ratio, respectively, between the common gain and the differential gain.

Abstract: It is disclosed a method for updating a cumulative residence time of a synchronization packet received at a node of a packet-switched communication network. The cumulative residence time is equal to a cumulative sum of residence times of the packet at nodes interposed between a further node which has generated the packet and the node. The node comprises an ingress circuit and an egress circuit. The method comprises: receiving the packet at the egress circuit from the ingress circuit; at a timestamp generator of the egress circuit, generating a timestamp; at the egress circuit, calculating a virtual timestamp based on the timestamp and on an estimated variable delay that will be undergone by the packet due to buffering in a buffer located downstream the timestamp generator; and, at the egress circuit, using the virtual timestamp for updating the cumulative residence time, before transmitting the packet to a still further node.

Abstract: Proposed is a method of decoding a differentially encoded PSK modulated optical data signal carrying FEC encoded data values. The optical signal is corrected by an estimated phase offset. From the corrected signal, respective likelihood values for the FEC encoded data values are derived, using an estimation algorithm which accounts for a differential encoding rule used for differentially encoding the optical signal. The derived likelihood values are limited to a predetermined range of values. From the limited likelihood values, FEC decoded data values are derived, using an algorithm which accounts for a FEC encoding rule used for FEC encoding the FEC encoded data values.

Abstract: Proposed is a method of decoding a differentially encoded PSK modulated optical data signal carrying FEC encoded data values. The optical signal is corrected by an estimated phase offset. From the corrected signal, respective likelihood values for the FEC encoded data values are derived, using an estimation algorithm which accounts for a differential encoding rule used for differentially encoding the optical signal. The derived likelihood values are limited to a predetermined range of values. From the limited likelihood values, FEC decoded data values are derived, using an algorithm which accounts for a FEC encoding rule used for FEC encoding the FEC encoded data values.

Abstract: It is disclosed an optical coherent receiver for an optical communication network. The optical coherent receiver is configured to receive a modulated optical signal and to process it for generating an in-phase component and a quadrature component. The optical coherent receiver comprises a power adjuster in turn comprising a multiplying unit and a retroactively connected digital circuit. The multiplying unit is configured to multiply the in-phase and quadrature components by in-phase and quadrature gains, respectively, thereby providing power-adjusted in-phase and quadrature components. The digital circuit is configured to compute: a common gain indicative of a sum of the powers of the power-adjusted in-phase and quadrature components; a differential gain indicative of a difference between the powers of the power-adjusted in-phase and quadrature components; and the in-phase and quadrature gains as a product and a ratio, respectively, between the common gain and the differential gain.

Abstract: Equipment protection of a switch matrix (SM) in a network node, which contains a number of matrix modules (M1.1-M4.4, E1.5-E4.6) is achieved by slicing an input signal into k parallel signal slices (x(0)-x(3)) with k>2; coding the k signal slices into a number of n coded signal slices (x(0)-x(5)) with n>k+1 using an error correcting code to add redundancy to said input signal; switching said n coded signal slices through the switching matrix (SM) via n distinct matrix modules; and decoding the n coded signal slices into k decoded signal slices to correct errors introduced while passing through said switch matrix. Preferably, the switch matrix (SM) contains a first number of matrix boards (MB1-MB4, EB5, EB6), each carrying a second number of matrix modules (M1.1-M4.4, E1.5-E4.6). The n coded signal slices are switched via matrix modules on n distinct matrix boards.

Abstract: A golf tee includes a stem defining a first end and a second end. The golf tee includes a ball receiving portion positioned on the second end of the stem. A level gauge is disposed in the ball receiving portion. The stem includes indicia representative of a depth of insertion of the first end into a surface.

Abstract: It is disclosed a method for updating a cumulative residence time of a synchronization packet received at a node of a packet-switched communication network. The cumulative residence time is equal to a cumulative sum of residence times of the packet at nodes interposed between a further node which has generated the packet and the node. The node comprises an ingress circuit and an egress circuit. The method comprises: receiving the packet at the egress circuit from the ingress circuit; at a timestamp generator of the egress circuit, generating a timestamp; at the egress circuit, calculating a virtual timestamp based on the timestamp and on an estimated variable delay that will be undergone by the packet due to buffering in a buffer located downstream the timestamp generator; and, at the egress circuit, using the virtual timestamp for updating the cumulative residence time, before transmitting the packet to a still further node.

Abstract: A method of processing information packets is disclosed which is adapted for a telecommunication apparatus comprising first processing means, second processing means and memory means. This method comprises the steps of: A) receiving an information packet from a telecommunication network by means of the first processing means; B) checking whether the value of a predetermined characteristic of this packet has already been processed by the second processing means; C) if the check at step B) is negative, checking whether this value has already been stored into the memory means; and D) if the check at step C) is negative, transmitting this value from the first processing means to the memory means and storing this value into the memory means. This method can advantageously be used in a telecommunication apparatus, particularly a layer-2 switch machine.

Abstract: Equipment protection of a switch matrix (SM) in a network node, which contains a number of matrix modules (M1.1-M4.4, E1.5-E4.6) is achieved by slicing an input signal into k parallel signal slices (x(0)-x(3)) with k>2; coding the k signal slices into a number of n coded signal slices (x(0)-x(5)) with n>k+1 using an error correcting code to add redundancy to said input signal; switching said n coded signal slices through the switching matrix (SM) via n distinct matrix modules; and decoding the n coded signal slices into k decoded signal slices to correct errors introduced while passing through said switch matrix. Preferably, the switch matrix (SM) contains a first number of matrix boards (MB1-MB4, EB5, EB6), each carrying a second number of matrix modules (M1.1-M4.4, E1.5-E4.6). The n coded signal slices are switched via matrix modules on n distinct matrix boards.

Abstract: It is disclosed a method for decoding an information word from a set of coded words. The method comprises the steps of receiving a coded word, of selecting a coded word having the minimum distance from the received coded word from a pre-configured sub-set of the set of the coded words, wherein the sub-set is configured to at least two coded words having each other a distance higher than the minimum distance between the coded words of the set, and of decoding the information word from the selected coded word.

Abstract: A method of processing information packets is disclosed which is adapted for a telecommunication apparatus comprising first processing means, second processing means and memory means. This method comprises the steps of: A) receiving an information packet from a telecommunication network by means of the first processing means; B) checking whether the value of a predetermined characteristic of this packet has already been processed by the second processing means; C) if the check at step B) is negative, checking whether this value has already been stored into the memory means; and D) if the check at step C) is negative, transmitting this value from the first processing means to the memory means and storing this value into the memory means. This method can advantageously be used in a telecommunication apparatus, particularly a layer-2 switch machine.

Abstract: A method and apparatus for interfacing a parallel connection, the parallel connection transmitting high bit-rate signals for a short distance. The method comprises: receiving a synchronous N-bits input data flow at a first input frequency; inserting said input data flow into parallel packets having a given length; and outputting said packets having a given length at a second output frequency onto a M-wires parallel connection.