Abstract: The circuit system includes an integrated circuit which is one of a family of equivalent integrated circuits that comprises a first-generation integrated circuit operating at the supply voltage of the circuit system and at least one subsequent-generation integrated circuit having a portion operating at a lower voltage. The first-generation integrated circuit has a direct electrical connection between one of the supply terminals and another terminal. The subsequent-generation integrated circuit has a voltage reducer with regulator the output of which is connected to the other terminal. A filter capacitor is connected between the other terminal and one of the supply terminals.

Abstract: Testing a CMOS integrated circuit includes establishing a current threshold value, powering the integrated circuit in static and idle conditions, measuring the current absorbed by the integrated circuit and comparing this with the threshold value and accepting or rejecting the integrated circuit if the comparison shows that the current absorbed measured is respectively lower or higher than the threshold value. To improve discrimination between non-faulty and faulty devices, the threshold value is obtained by forming two measurement transistors in the integrated circuit, one n channel and the other p channel, biasing these in the cut-off zone and measuring their sub-threshold currents.

Abstract: A method of testing an integrated circuit that includes supplying the integrated circuit in static conditions; biasing the p-type body regions with a potential more negative than the negative pole of the supply and the n-type body regions with a potential more positive than the positive pole of the supply; setting a current threshold value; measuring the current absorbed; comparing the current measured with the threshold current; and accepting or rejecting the integrated circuit if the comparison shows that the current measured is less than or is greater than the threshold value, respectively.

Abstract: Testing a CMOS integrated circuit includes establishing a current threshold value, powering the integrated circuit in static and idle conditions, measuring the current absorbed by the integrated circuit and comparing this with the threshold value and accepting or rejecting the integrated circuit if the comparison shows that the current absorbed measured is respectively lower or higher than the threshold value. To improve discrimination between non-faulty and faulty devices, the threshold value is obtained by forming two measurement transistors in the integrated circuit, one n channel and the other p channel, biasing these in the cut-off zone and measuring their sub-threshold currents.

Abstract: The circuit system includes an integrated circuit which is one of a family of equivalent integrated circuits that comprises a first-generation integrated circuit operating at the supply voltage of the circuit system and at least one subsequent-generation integrated circuit having a portion operating at a lower voltage. The first-generation integrated circuit has a direct electrical connection between one of the supply terminals and another terminal. The subsequent-generation integrated circuit has a voltage reducer with regulator the output of which is connected to the other terminal. A filter capacitor is connected between the other terminal and one of the supply terminals.

Abstract: A cell library for the design of integrated circuits, for example using CMOS technology, includes cells which define circuit modules in rectangular areas having an identical side. Two traces are provided which extend at right-angles to the identical side and which define strips for connection to the supply, at least one of which is in contact with the source regions of MOS transistors of a CMOS pair. In order to permit the design of integrated circuits in which the analog parts are insensitive to the noise induced in the substrate by the digital parts and in which it is possible to reduce the current absorption of the digital parts in stand-by mode, the cell library also provides a group of cells in which there is provided at least one additional trace which defines an additional strip for connection to the outside and which is in contact with the body regions of the MOS transistors of the CMOS pair.

Abstract: A digital circuit for controlling the gain of an amplifier stage of a coded signal receiving channel is provided. The circuit includes a peak detector coupled to the input terminal of the receiving channel through a coded signal rectifying circuit and a gain control stage. The gain control stage includes a digital comparator having two input terminals respectively connected to an output terminal of the peak detector and to a memory, and an output terminal coupled to a gain control terminal of the amplifier stage. The address selectable contents of the memory contain predetermined peak values in coded form.

Abstract: In a CMOS logic circuit destined to function at a relatively high supply voltage such as to require the formation of graded diffusions in the structure of N-MOS transistors, a NAND configuration is used which comprises a staked pair of N-MOS transistors. This permits to restrict the number of graded diffusions to be formed in N-MOS structures only to the drain regions which are directly connected to an output node. In clocked CMOS circuitry where transfer transistors are normally used between gates, the advantages in terms of enhanced speed and ability of the circuit to be compacted by cutting the number of N-MOS structures necessarily provided with drain extension regions as in prior art circuits, are remarkable.

Abstract: Latch-up in two supplies (+VCC and -VBB) CMOS integrated circuits is prevented by means of a single integrated protection MOS transistor, N-channel for P-Well CMOS or P-channel for N-Well CMOS, having its drain (source) connected to ground and its body region, gate and source (drain) connected to -VBB (+VCC). The desired threshold voltage and dimensions of the protection transistor do not present particular problems of implementation.

Abstract: A noise suppression interface circuit, using field effect transistors of MOS type, for non-superimposed two-phase timing signal generators is described. The upper level and the lower level of the output timing signals are determined by the potentials of two circuit nodes (V.sub.H, V.sub.L) which are respectively coupled, by a first transistor (M1) and a second transistor (M2), operating at saturation, to a first supply terminal (+V.sub.DD) and a second supply terminal (-V.sub.SS) having potentials which are respectively equal and opposite to a common potential. The circuit nodes (V.sub.H, V.sub.L) are both coupled to the common potential by identical number of transistors (M3, M4; M5, M6) each coupled in a diode configuration.