Abstract: A label-switching and control interface for asynchronous fast-packet switching consisting of a set of label-switching and cell-processing units controlled by a suitable control unit. The units operate at each multiplex level in real time thanks to a microprogrammed logic requiring the control processor intervention only at the connection set-up/release. The units implement the low levels of the flow control algorithms necessary to conveniently exploit the advantages of the techniques. The label becomes indicative of a virtual circuit which is allotted only locally to the call, annulling thus the necessity of very extensive labels, while the parameters which characterize the connection which uses a particular label are stored in the unit itself.

Abstract: An interface interposed between a PCM data terminal and a processor comprises a bus accessor dialoguing with the processor, input and output circuitry coupled to the terminal, and intervening logic circuits and data stores designed to supply the processor in a time-division mode with preprocessed messages received or to be transmitted over a multiplicity of channels. The interface is operable according to dialogue procedures of HDLC type such as those corresponding to CCITT recommendations X25, X75 and N. 7, with switchover from one protocol to another.

Abstract: An apparatus for handling incoming signals from sensors monitoring the state of certain points of a telephone circuit as well as outgoing signals for drivers associated with other circuit points includes a preprocessor PE inserted between the assembly DR of sensors and drivers, on the one hand, and a processor EL, on the other hand. The preprocessor and the processor have access, through a bus 5, to a common memory ME having areas allocated to the scanning of the circuit points, to time-counting operations and to the storage of messages from the preprocessor. A microprogram memory in the preprocessor, when addressed by a sequencer CM started automatically, manually or in response to an instruction from the processor, initiates a temporary seizure of the bus--if the latter is available--whereupon an initial address is delivered from the common memory ME to a working memory ML in the preprocessor to start the scanning of successive pairs of circuit points.