Patents by Inventor Carlo E. Barrientos

Carlo E. Barrientos has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for constructing a global interconnect model of a device having ambiguous submodule abutments
    Patent number: 6820247
    Abstract: A method for constructing a global interconnect model of a device having ambiguous abutments between submodules includes generating a discrete model for each of the submodules, identifying interconnections between the submodules, and defining a plurality of global abutment points for the interconnections between the submodules. Each global abutment point specifies a locus of interconnection points along at least a portion of a boundary of a particular one of the submodules. The discrete models are stitched together based on the global abutment points to construct a global model.
    Type: Grant
    Filed: June 14, 2000
    Date of Patent: November 16, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Carlo E. Barrientos, Peter J. Hannan, Christopher C. Sander
  • Method and apparatus for specifying global abutment points in a semiconductor device having ambiguous submodule abutments
    Patent number: 6546533
    Abstract: A method for designing a circuit having a plurality of submodules includes providing a floor plan for the circuit. The floor plan defines boundaries for each of the submodules. A component list identifying internal circuit elements of the submodules and interconnections between the internal circuit elements is provided. A plurality of global abutment points are defined for the interconnections between internal circuit elements of different submodules. Each global abutment point specifies a locus of interconnection points along at least a portion of the boundary of a particular one of the submodules. A program storage device includes a floor plan database, a connectivity database, and program instructions. The floor plan database is adapted to store a floor plan of a circuit having a plurality of submodules. The floor plan defines boundaries for each of the submodules.
    Type: Grant
    Filed: June 14, 2000
    Date of Patent: April 8, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Carlo E. Barrientos, Rudy J. Albachten, III, Dean Marvin
  • Method for performing floorplan timing analysis using multi-dimensional feedback in a spreadsheet with computed hyperlinks to physical layout graphics and integrated circuit made using same
    Patent number: 5910899
    Abstract: A computer-implemented method for aiding in the design of an integrated circuit (IC) floorplan. The method comprises receiving a netlist, physical layout information, and timing constraints of the IC and performing timing analysis of the signal paths of the IC. The user selects the set of nets to by analyzed. The timing analysis comprises calculating net delays as a function of the length of the signal paths. The timing analysis further comprises calculating slack times by subtracting from the clock cycle time of the IC the sum of the driven at timing constraint, the needed by timing constraint, and the net delay. Paths which have a slack time greater than a slack failure value are passing nets and paths which have a slack time greater than a slack failure value are failing nets. The slack failure value is user-specifiable and defaults to zero.
    Type: Grant
    Filed: October 25, 1996
    Date of Patent: June 8, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Carlo E. Barrientos
  • Method for performing floorplan timing analysis by selectively displaying signal paths based on slack time calculations and integrated circuit made using same
    Patent number: 5903472
    Abstract: A computer-implemented method for aiding in the design of an integrated circuit (IC) floorplan. The method comprises receiving a netlist, physical layout information, and timing constraints of the IC and performing timing analysis of the signal paths of the IC. The user selects the set of nets to by analyzed. The timing analysis comprises calculating net delays as a function of the length of the signal paths. The timing analysis further comprises calculating slack times by subtracting from the clock cycle time of the IC the sum of the driven at timing constraint, the needed by timing constraint, and the net delay. Paths which have a slack time greater than a slack failure value are passing nets and paths which have a slack time greater than a slack failure value are failing nets. The slack failure value is user-specifiable and defaults to zero.
    Type: Grant
    Filed: October 25, 1996
    Date of Patent: May 11, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Carlo E. Barrientos
  • Method for performing floorplan timing analysis using multi-dimensional feedback in a histogram and integrated circuit made using same
    Patent number: 5896301
    Abstract: A computer-implemented method for aiding in the design of an integrated circuit (IC) floorplan. The method comprises receiving a netlist, physical layout information, and timing constraints of the IC and performing timing analysis of the signal paths of the IC. The user selects the set of nets to by analyzed. The timing analysis comprises calculating net delays as a function of the length of the signal paths. The timing analysis further comprises calculating slack times by subtracting from the clock cycle time of the IC the sum of the driven at timing constraint, the needed by timing constraint, and the net delay. Paths which have a slack time greater than a slack failure value are passing nets and paths which have a slack time greater than a slack failure value are failing nets. The slack failure value is user-specifiable and defaults to zero.
    Type: Grant
    Filed: October 25, 1996
    Date of Patent: April 20, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Carlo E. Barrientos