Abstract: A low-dropout regulator with inrush current limiting capabilities may include an output terminal to provide an output signal, a first current branch comprising a pass device connected to the output terminal, and a second current branch comprising a driver transistor and a current generator. The low-dropout regulator may further include an error amplifier to control the driver transistor. The error amplifier may have a first input node to apply a reference signal, and a second input node coupled to the output terminal. The low-dropout regulator may include a current mirror to couple the second current branch to the first current branch. The current mirror is configured to mirror a current in the second current branch to the output current branch.

Abstract: A voltage regulator comprises an output transistor with a controlled section connected between a first supply terminal and an output terminal. An amplifier comprises a reference input and a feedback input. A current mirror comprising a replica transistor. The current mirror is configured to mirror and attenuate a load current supplied by the output transistor to the replica transistor. A filter circuit is coupled to a controlled section of the replica transistor and coupled to the feedback input of the amplifier via the output terminal.

Abstract: An amplifier circuit includes a circuit path of serially connected complementary type transistors. First and second feedback loops include a loop amplifier, the transistors of the circuit path and a corresponding resistor.

Abstract: A low-dropout regulator having an output current branch being arranged between a supply line to provide a supply potential and an output node to provide a regulated output voltage. The output current branch includes an output driver to provide an output current at the output node. The output driver has a control connection to apply a control voltage to operate the output driver with a different conductivity in dependence on the control voltage. The LDO includes an input amplifier stage to provide the control voltage to the control connection of the output driver. The input amplifier stage is configured to provide the control voltage with a different slew rate in dependence on an increase or decrease of the output current.

Abstract: A voltage regulator comprises an output transistor with a controlled section connected between a first supply terminal and an output terminal. An amplifier comprises a reference input and a feedback input. A current mirror comprising a replica transistor. The current mirror is configured to mirror and attenuate a load current supplied by the output transistor to the replica transistor. A filter circuit is coupled to a controlled section of the replica transistor and coupled to the feedback input of the amplifier via the output terminal.

Abstract: An amplifier circuit includes a circuit path of serially connected complementary type transistors. First and second feedback loops include a loop amplifier, the transistors of the circuit path and a corresponding resistor.

Abstract: A low-dropout regulator comprises an output current branch (100) in which a first output driver (110) and a second output driver (120) is arranged. An input amplifier stage (200) provides a first control current (I1) to control the operating state of the first and the second output driver (110, 120). A current generator unit (300) provides a second control current (12) to operate the first output driver (110) in the second operating state and provides a third control current (13) to operate the second output driver (120) in the second operating state, when the first control current (I1) of the input amplifier stage (200) is below a threshold level.

Abstract: A low-dropout regulator comprises an output current branch (100) in which a first output driver (110) and a second output driver (120) is arranged. An input amplifier stage (200) provides a first control current (I1) to control the operating state of the first and the second output driver (110, 120). A current generator unit (300) provides a second control current (12) to operate the first output driver (110) in the second operating state and provides a third control current (13) to operate the second output driver (120) in the second operating state, when the first control current (I1) of the input amplifier stage (200) is below a threshold level.

Abstract: A low-dropout regulator comprises an output current branch (10) being arranged between a supply line (Vsupply) to provide a supply potential (VDD) and an output node (O) to provide a regulated output voltage (Vreg). The output current branch (10) comprises an output driver (20) to provide an output current (Iout) at the output node (O). The output driver (20) has a control connection (G20) to apply a control voltage (Vc) to operate the output driver (20) with a different conductivity in dependence on the control voltage (Vc). The LDO comprises an input amplifier stage (30) to provide the control voltage (Vc) to the control connection (G20) of the output driver (20). The input amplifier stage (30) is configured to provide the control voltage (Vc) with a different slew rate in dependence on an increase or decrease of the output current (Iout).

Abstract: A level shift regulator circuit comprises a level shift transistor (Mls) and an output transistor (Mreg) being arranged in series to the level shift transistor (Mls) in an output path (OP). The circuit comprises a feedback path (FP) being arranged between an input node (IN) of the output path (OP) and a gate connection of the output transistor (Mreg). A current splitter (CS) is provided to split a current of a current source (IS0) coupled to the input node (IN) to reduce the loop gain. A current mirror (CM) is arranged in series to the current splitter (CS) to reduce the signal current provided by the current splitter (CS) to the gate connection of the output transistor (Mreg) to further reduce the gain and to improve stability of the circuit. A first and second filter (F1, F2) may optionally be provided to improve the phase response.

Abstract: A level shift regulator circuit comprises a level shift transistor (Mls) and an output transistor (Mreg) being arranged in series to the level shift transistor (Mls) in an output path (OP). The circuit comprises a feedback path (FP) being arranged between an input node (IN) of the output path (OP) and a gate connection of the output transistor (Mreg). A current splitter (CS) is provided to split a current of a current source (ISO) coupled to the input node (IN) to reduce the loop gain. A current mirror (CM) is arranged in series to the current splitter (CS) to reduce the signal current provided by the current splitter (CS) to the gate connection of the output transistor (Mreg) to further reduce the gain and to improve stability of the circuit. A first and second filter (F1, F2) may optionally be provided to improve the phase response.

Abstract: A low dropout regulator comprises an output transistor with a controlled section between a first supply terminal and an output terminal, and a differential amplifier comprising a feedback input coupled to the output terminal, a reference input receiving a reference voltage, an output connected to a control terminal of the output transistor, and a pair of input transistors connected to a tail current source. A control terminal of a first transistor is connected to the reference input. A control terminal of a second transistor is connected to the feedback input. A first capacitive element is coupled between the output terminal and common connection of the input transistors of one pair with their tail current source. A second capacitive element is coupled between a second supply terminal and the common connection of the input transistors of one pair with their tail current source.

Abstract: In one embodiment a low-dropout regulator comprises a first differential amplifier (Nmos1) to receive an input voltage (Vin), a power transistor (T1) coupled to the first differential input pair (Nmos1), the power transistor having an output (OUT) forming an output terminal of the low-dropout regulator to provide an output voltage (Vout) as a function of the input voltage (Vin), a second differential amplifier (Pmos1) coupled to the first differential amplifier (Nmos1), and a switching element (Mncut1, Mncut2) coupled between first and second differential amplifier (Nmos1, Pmos1), said switching element (Mncut1, Mncut2) being operated as a function of a feedback signal (Sfb) derived from the output voltage (Vout). The second differential amplifier (Pmos1) is complementary to the first differential amplifier (Nmos1).

Abstract: In one embodiment a low-dropout regulator comprises a first differential amplifier (Nmos1) to receive an input voltage (Vin), a power transistor (T1) coupled to the first differential input pair (Nmos1), the power transistor having an output (OUT) forming an output terminal of the low-dropout regulator to provide an output voltage (Vout) as a function of the input voltage (Vin), a second differential amplifier (Pmos1) coupled to the first differential amplifier (Nmos1), and a switching element (Mncut1, Mncut2) coupled between first and second differential amplifier (Nmos1, Pmos1), said switching element (Mncut1, Mncut2) being operated as a function of a feedback signal (Sfb) derived from the output voltage (Vout). The second differential amplifier (Pmos1) is complementary to the first differential amplifier (Nmos1).

Abstract: A low dropout regulator comprises an output transistor (MPOUT) with a controlled section coupled between a first supply terminal (VS) and an output terminal (OUT), and a differential amplifier that comprises a feedback input (VFB) coupled to the output terminal (OUT), a reference input (VR) for receiving a reference voltage, an output (DOUT) connected to a control terminal of the output transistor (MPOUT), and at least one pair of input transistors (M1, M2, M1a, M2a, M1b, M2b). The input transistors (M1, M2, M1a, M2a, M1b, M2b) of each pair are commonly connected to a tail current source (Iab, Ia, Ib) of the respective pair. A control terminal of a respective first transistor (M1, M1a, M1b) of each pair is connected to the reference input (VR). A control terminal of a respective second transistor (M2, M2a, M2b) of each pair is connected to the feedback input (VFB).

Abstract: A control circuit arrangement for pulse-width modulated DC/DC converters includes a phase generator for a complementary driver which provides respective gate signals to a first and second driver transistor in response to a control signal. A clock control circuit receives a clock signal and a pulse-width modulated signal and provides the control signal in response to a signal edge of the pulse-width modulated signal and the clock signal applied thereto. A mode selection input terminal receives a mode selection signal to select a first mode or a second mode of operation. The phase generator provides in the first mode each of the gate signals the control signal and the respective other gate signal. In the second mode of operation, it provides each gate signal in response to the control signal.

Abstract: An amplifier with a non-linear current mirror comprises an amplification stage having an input terminal for an input signal as well as an output stage coupled to the amplification stage by a current mirror stage. The current mirror stage comprises at least one mirror transistor coupled to the amplification stage and at least one output transistor coupled to the output stage. The amplifier comprises two variable resistive elements, each of them connected in series to one of the mirror transistor and the output transistor. A tuning stage is adapted to tune the variable resistive elements in response to the input signal.

Abstract: A control circuit arrangement for pulse-width modulated DC/DC converters includes a phase generator for a complementary driver which provides respective gate signals to a first and second driver transistor in response to a control signal. A clock control circuit receives a clock signal and a pulse-width modulated signal and provides the control signal in response to a signal edge of the pulse-width modulated signal and the clock signal applied thereto. A mode selection input terminal receives a mode selection signal to select a first mode or a second mode of operation. The phase generator provides in the first mode each of the gate signals the control signal and the respective other gate signal. In the second mode of operation, it provides each gate signal in response to the control signal.

Abstract: A voltage regulator, comprising: an input terminal; an output terminal at which an output voltage is provided; an output transistor which couples the input terminal of the voltage regulator to the output terminal of the voltage regulator; and a transimpedance amplifier including an input terminal which is coupled to the output terminal of the voltage regulator and an output terminal which is coupled to a control terminal of the output transistor, optionally via a coupling, the coupling having an impedance value between the output terminal of the transimpedance amplifier and the control terminal of the output transistor which at a given frequency is smaller than or equal to an impedance value of an output impedance of the transimpedance amplifier.

Abstract: An amplifier with a non-linear current mirror comprises an amplification stage having an input terminal for an input signal as well as an output stage coupled to the amplification stage by a current mirror stage. The current mirror stage comprises at least one mirror transistor coupled to the amplification stage and at least one output transistor coupled to the output stage. The amplifier comprises two variable resistive elements, each of them connected in series to one of the mirror transistor and the output transistor. A tuning stage is adapted to tune the variable resistive elements in response to the input signal.