Abstract: A method of manufacturing a semiconductor device is described. The method includes depositing a photoresist layer over a semiconductor substrate. The photoresist layer is patterned to form an opening in the photoresist layer. A copper pillar is formed in the opening. A diffusion barrier layer is formed over the copper pillar and over a photoresist portion of the photoresist layer directly adjoining the opening. A solder structure is deposited over the diffusion barrier layer.

Abstract: A substrate includes a dielectric layer, a first metal bar, a plurality of first traces, a plurality of first openings, a second metal bar, and at least one second opening. The dielectric layer has a first major surface and a second major surface opposite to the first major surface. The first metal bar is on the first major surface. The plurality of first traces are on the first major surface. Each first trace is connected at one end to the first metal bar. The plurality of first openings expose the dielectric layer on the first major surface and intersect a first trace. The second metal bar is on the second major surface. The at least one second opening exposes the dielectric layer on the second major surface and intersects the second metal bar. The first openings are laterally offset with respect to the at least one second opening.

Abstract: A method of manufacturing a semiconductor device is described. The method includes depositing a photoresist layer over a semiconductor substrate. The photoresist layer is patterned to form an opening in the photoresist layer. A copper pillar is formed in the opening. A diffusion barrier layer is formed over the copper pillar and over a photoresist portion of the photoresist layer directly adjoining the opening. A solder structure is deposited over the diffusion barrier layer.

Abstract: A substrate includes a dielectric layer, a first metal bar, a plurality of first traces, a plurality of first openings, a second metal bar, and at least one second opening. The dielectric layer has a first major surface and a second major surface opposite to the first major surface. The first metal bar is on the first major surface. The plurality of first traces are on the first major surface. Each first trace is connected at one end to the first metal bar. The plurality of first openings expose the dielectric layer on the first major surface and intersect a first trace. The second metal bar is on the second major surface. The at least one second opening exposes the dielectric layer on the second major surface and intersects the second metal bar. The first openings are laterally offset with respect to the at least one second opening.

Abstract: A substrate and method of fabrication is disclosed. In one example, the substrate includes a first dielectric layer, a first and a second conductive trace arranged over the first dielectric layer and a second dielectric layer arranged between the first and second conductive traces and partially covering the first and second conductive traces, wherein an exposed part of the first and second conductive traces is exposed from the second dielectric layer at an interface and wherein a shape of the interface between the first and second conductive traces includes one or more of an angle, an edge, a curvature, a bulge, a step and an indentation.

Abstract: A substrate and method of fabrication is disclosed. In one example, the substrate includes a first dielectric layer, a first and a second conductive trace arranged over the first dielectric layer and a second dielectric layer arranged between the first and second conductive traces and partially covering the first and second conductive traces, wherein an exposed part of the first and second conductive traces is exposed from the second dielectric layer at an interface and wherein a shape of the interface between the first and second conductive traces includes one or more of an angle, an edge, a curvature, a bulge, a step and an indentation.

Abstract: A semiconductor package includes a plurality of contact areas having a specific contact area and a plurality of solder balls applied to the contact areas. Two or more specific solder balls are applied to the specific contact area, and a minimum distance between the two specific solder balls is set such that the two or more specific solder balls merge into one another when connecting them to a substrate in a reflow process.

Abstract: A method of connecting a semiconductor package to a board includes providing a board having a plurality of contact regions, providing a semiconductor package having a plurality of contact areas, selecting a specific contact area out of the plurality of contact areas, applying solder balls to the contact areas and therein applying two or more specific solder balls to the specific contact area, and connecting the semiconductor package to the board in such a way that the two or more specific solder balls are connected with each other and with a contact region of the plurality of contact regions of the board.

Abstract: A method of connecting a semiconductor package to a board includes providing a board having a plurality of contact regions, providing a semiconductor package having a plurality of contact areas, selecting a specific contact area out of the plurality of contact areas, applying solder balls to the contact areas and therein applying two or more specific solder balls to the specific contact area, and connecting the semiconductor package to the board in such a way that the two or more specific solder balls are connected with each other and with a contact region of the plurality of contact regions of the board.