Patents by Inventor Carlo Musilli
Carlo Musilli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8891309Abstract: Read failure is reduced by increasing the drain current through a serial string of memory cells during the read operation. In one embodiment, this is accomplished by using a higher read pass voltage for unselected word lines when the selected word line is within a predetermined distance of the drain side of the memory block array. If the selected word line is closer to the source side, a lower read pass voltage is used. In another embodiment, the cells on the word lines closer to the drain side of the memory block array are erased to a lower threshold voltage than the memory cells on the remaining word lines.Type: GrantFiled: October 13, 2011Date of Patent: November 18, 2014Assignee: Micron Technology, Inc.Inventors: Seiichi Aritome, Alessandro Torsi, Carlo Musilli
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Patent number: 8705290Abstract: Some embodiments include methods and devices having a module and memory cells. The module is configured to reduce the amount of electrons in the sources and drains of the memory cells during a programming operation.Type: GrantFiled: September 15, 2012Date of Patent: April 22, 2014Assignee: Micron Technology, Inc.Inventors: Prashant S. Damle, Krishna K. Parat, Alessandro Torsi, Carlo Musilli, Kalpana Vakati, Akira Goda
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Patent number: 8610490Abstract: Voltage switches, memory devices, memory systems, and methods for switching are disclosed. One such voltage switch uses a pair of switch circuits coupled in series, each switch circuit being driven by a level shift circuit. Each switch circuit uses a group of series coupled transistors with a parallel control transistor where the number of transistors in each group may be determined by an expected switch input voltage and a maximum allowable voltage drop for each transistor. A voltage of a particular state of an enable signal is shifted up to the switch input voltage by the level shift circuits. The particular state of the enable signal turns on the voltage switch such that the switch output voltage is substantially equal to the switch input voltage.Type: GrantFiled: March 25, 2013Date of Patent: December 17, 2013Assignee: Micron Technology, Inc.Inventors: Giulio G. Marotta, Carlo Musilli, Stefano Perugini, Alessandro Torsi, Tommaso Vali
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Patent number: 8565018Abstract: A method for programming includes initially biasing a subset of a plurality of control gates of a string of memory cells with a negative voltage, wherein the subset is less than all of the plurality of control gates of the string. The control gate of a selected memory cell is subsequently biased with a programming voltage during a programming phase.Type: GrantFiled: June 1, 2012Date of Patent: October 22, 2013Assignee: Micron Technology, Inc.Inventors: Akira Goda, Alessandro Torsi, Carlo Musilli, Mark A. Helm, Doyle Rivers
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Patent number: 8405444Abstract: Voltage switches, memory devices, memory systems, and methods for switching are disclosed. One such voltage switch uses a pair of switch circuits coupled in series, each switch circuit being driven by a level shift circuit. Each switch circuit uses a group of series coupled transistors with a parallel control transistor where the number of transistors in each group may be determined by an expected switch input voltage and a maximum allowable voltage drop for each transistor. A voltage of a particular state of an enable signal is shifted up to the switch input voltage by the level shift circuits. The particular state of the enable signal turns on the voltage switch such that the switch output voltage is substantially equal to the switch input voltage.Type: GrantFiled: July 5, 2012Date of Patent: March 26, 2013Assignee: Micron Technology, Inc.Inventors: Giulio G. Marotta, Carlo Musilli, Stefano Perugini, Alessandro Torsi, Tommaso Vali
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Publication number: 20130016569Abstract: Some embodiments include methods and devices having a module and memory cells. The module is configured to reduce the amount of electrons in the sources and drains of the memory cells during a programming operation.Type: ApplicationFiled: September 15, 2012Publication date: January 17, 2013Applicant: Micron Technology, Inc.Inventors: Prashant S. Damle, Krishna Parat, Alessandro Torsi, Carlo Musilli, Kalpana Vakati, Akira Goda
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Patent number: 8331160Abstract: Some embodiments include methods and devices having a module and memory cells. The module is configured to reduce the amount of electrons in the sources and drains of the memory cells during a programming operation.Type: GrantFiled: July 28, 2011Date of Patent: December 11, 2012Assignee: Micron Technology, Inc.Inventors: Prashant S. Damle, Krishna Parat, Alessandro Torsi, Carlo Musilli, Kalpana Vakati, Akira Goda
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Publication number: 20120269011Abstract: Voltage switches, memory devices, memory systems, and methods for switching are disclosed. One such voltage switch uses a pair of switch circuits coupled in series, each switch circuit being driven by a level shift circuit. Each switch circuit uses a group of series coupled transistors with a parallel control transistor where the number of transistors in each group may be determined by an expected switch input voltage and a maximum allowable voltage drop for each transistor. A voltage of a particular state of an enable signal is shifted up to the switch input voltage by the level shift circuits. The particular state of the enable signal turns on the voltage switch such that the switch output voltage is substantially equal to the switch input voltage.Type: ApplicationFiled: July 5, 2012Publication date: October 25, 2012Applicant: Micron Technology, Inc.Inventors: Giulio G. Marotta, Carlo Musilli, Stefano Perugini, Alessandro Torsi, Tommaso Vali
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Publication number: 20120236640Abstract: A method for programming includes initially biasing a subset of a plurality of control gates of a string of memory cells with a negative voltage, wherein the subset is less than all of the plurality of control gates of the string. The control gate of a selected memory cell is subsequently biased with a programming voltage during a programming phase.Type: ApplicationFiled: June 1, 2012Publication date: September 20, 2012Inventors: Akira Goda, Alessandro Torsi, Carlo Musilli, Mark A. Helm, Doyle Rivers
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Patent number: 8217705Abstract: Voltage switches, memory devices, memory systems, and methods for switching are disclosed. One such voltage switch uses a pair of switch circuits coupled in series, each switch circuit being driven by a level shift circuit. Each switch circuit uses a group of series coupled transistors with a parallel control transistor where the number of transistors in each group may be determined by an expected switch input voltage and a maximum allowable voltage drop for each transistor. A voltage of a particular state of an enable signal is shifted up to the switch input voltage by the level shift circuits. The particular state of the enable signal turns on the voltage switch such that the switch output voltage is substantially equal to the switch input voltage.Type: GrantFiled: May 6, 2010Date of Patent: July 10, 2012Assignee: Micron Technology, Inc.Inventors: Giulio G. Marotta, Carlo Musilli, Stefano Perugini, Alessandro Torsi, Tommaso Vali
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Patent number: 8203876Abstract: Methods for programming and memory devices are disclosed. One such method for programming includes initially biasing a subset of a plurality of control gates of a string of memory cells with a negative voltage, wherein the subset is less than all of the plurality of control gates of the string. The control gate of a selected memory cell is subsequently biased with a programming voltage during a programming phase.Type: GrantFiled: December 1, 2009Date of Patent: June 19, 2012Assignee: Micron Technology, Inc.Inventors: Akira Goda, Alessandro Torsi, Carlo Musilli, Mark A. Helm, Doyle Rivers
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Patent number: 8164950Abstract: A punch-through disturb effect in a memory device can be reduced by biasing a selected word line at a program voltage to program a selected memory cell, biasing word lines on the drain side of the series string with a Vpass voltage, turning off an adjacent memory cell to the selected memory cell, and biasing remaining word lines on the source side of the turned-off memory cell with a Vlow voltage that is less than Vpass.Type: GrantFiled: May 12, 2010Date of Patent: April 24, 2012Assignee: Micron Technology, Inc.Inventors: Alessandro Torsi, Carlo Musilli, Seiichi Aritome
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Publication number: 20120051139Abstract: Read failure is reduced by increasing the drain current through a serial string of memory cells during the read operation. In one embodiment, this is accomplished by using a higher read pass voltage for unselected word lines when the selected word line is within a predetermined distance of the drain side of the memory block array. If the selected word line is closer to the source side, a lower read pass voltage is used. In another embodiment, the cells on the word lines closer to the drain side of the memory block array are erased to a lower threshold voltage than the memory cells on the remaining word lines.Type: ApplicationFiled: October 13, 2011Publication date: March 1, 2012Inventors: Seiichi ARITOME, Alessandro TORSI, Carlo MUSILLI
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Publication number: 20110280085Abstract: Some embodiments include methods and devices having a module and memory cells. The module is configured to reduce the amount of electrons in the sources and drains of the memory cells during a programming operation.Type: ApplicationFiled: July 28, 2011Publication date: November 17, 2011Inventors: Prashant S. Damle, Krishna Parat, Alessandro Torsi, Carlo Musilli, Kalpana Vakati, Akira Goda
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Patent number: 8059474Abstract: Read failure is reduced by increasing the drain current through a serial string of memory cells during the read operation. In one embodiment, this is accomplished by using a higher read pass voltage for unselected word lines when the selected word line is within a predetermined distance of the drain side of the memory block array. If the selected word line is closer to the source side, a lower read pass voltage is used. In another embodiment, the cells on the word lines closer to the drain side of the memory block array are erased to a lower threshold voltage than the memory cells on the remaining word lines.Type: GrantFiled: February 16, 2010Date of Patent: November 15, 2011Assignee: Micron Technology, Inc.Inventors: Seiichi Aritome, Alessandro Torsi, Carlo Musilli
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Publication number: 20110273219Abstract: Voltage switches, memory devices, memory systems, and methods for switching are disclosed. One such voltage switch uses a pair of switch circuits coupled in series, each switch circuit being driven by a level shift circuit. Each switch circuit uses a group of series coupled transistors with a parallel control transistor where the number of transistors in each group may be determined by an expected switch input voltage and a maximum allowable voltage drop for each transistor. A voltage of a particular state of an enable signal is shifted up to the switch input voltage by the level shift circuits. The particular state of the enable signal turns on the voltage switch such that the switch output voltage is substantially equal to the switch input voltage.Type: ApplicationFiled: May 6, 2010Publication date: November 10, 2011Inventors: Giulio G. Marotta, Carlo Musilli, Stefano Perugini, Alessandro Torsi, Tommaso Vali
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Patent number: 7990772Abstract: Some embodiments include methods and devices having a module and memory cells. The module is configured to reduce the amount of electrons in the sources and drains of the memory cells during a programming operation.Type: GrantFiled: March 11, 2009Date of Patent: August 2, 2011Assignee: Micron Technology Inc.Inventors: Prashant S. Damle, Krishna Parat, Alessandro Torsi, Carlo Musilli, Kalpana Vakati, Akira Goda
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Publication number: 20110128782Abstract: Methods for programming and memory devices are disclosed. One such method for programming includes initially biasing a subset of a plurality of control gates of a string of memory cells with a negative voltage, wherein the subset is less than all of the plurality of control gates of the string. The control gate of a selected memory cell is subsequently biased with a programming voltage during a programming phase.Type: ApplicationFiled: December 1, 2009Publication date: June 2, 2011Inventors: Akira Goda, Alessandro Torsi, Carlo Musilli, Mark A. Helm, Doyle Rivers
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Publication number: 20110116311Abstract: In one or more of the disclosed embodiments, a punch-through disturb effect in a memory device can be reduced by biasing a selected word line at a program voltage to program a selected memory cell, biasing word lines on the drain side of the series string with a Vpass voltage, turning off an adjacent memory cell to the selected memory cell, and biasing remaining word lines on the source side of the turned-off memory cell with a Vlow voltage that is less than Vpass.Type: ApplicationFiled: May 12, 2010Publication date: May 19, 2011Inventors: Alessandro Torsi, Carlo Musilli, Seiichi Aritome
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Publication number: 20100232234Abstract: Some embodiments include methods and devices having a module and memory cells. The module is configured to reduce the amount of electrons in the sources and drains of the memory cells during a programming operation.Type: ApplicationFiled: March 11, 2009Publication date: September 16, 2010Inventors: Prashant S. Damle, Krishna Parat, Alessandro Torsi, Carlo Musilli, Kalpana Vakati, Akira Goda