Abstract: The present invention relates to a segmented graphene nanoribbon, comprising at least two different graphene segments covalently linked to each other, each graphene segment having a monodisperse segment width, wherein the segment width of at least one of said graphene segments is 4 nm or less and to a method for preparing it by polymerizing at least one polycyclic aromatic monomer compound and/or at least one oligo phenylene aromatic hydrocarbon monomer compound to form at least one polymer and by at least partially cyclodehydrogenating the one or more polymer.

Abstract: The present invention relates to a segmented graphene nanoribbon, comprising at least two different graphene segments covalently linked to each other, each graphene segment having a monodisperse segment width, wherein the segment width of at least one of said graphene segments is 4 nm or less and to a method for preparing it by polymerizing at least one polycyclic aromatic monomer compound and/or at least one oligo phenylene aromatic hydrocarbon monomer compound to form at least one polymer and by at least partially cyclodehydrogenating the one or more polymer.

Abstract: The present invention provides a gate stack structure that has high mobilites and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010 charges/cm2 or less, a peak mobility of about 250 cm2/V-s or greater and substantially no mobility degradation at about 6.0×1012 inversion charges/cm2 or greater.

Abstract: The present invention provides a gate stack structure that has high mobilites and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010 charges/cm2 or less, a peak mobility of about 250 cm2/V-s or greater and substantially no mobility degradation at about 6.0×1012 inversion charges/cm2 or greater.