Abstract: An electric circuit includes a supply terminal to receive an outer supply voltage and a voltage regulator coupled to the supply terminal and to provide supply and resting voltages. A lock-out circuit is switchable between active and inactive states and receives the supply voltage at a supply node to generate, in the active state, an output voltage on a output terminal thereof. A protection circuit protects against electrostatic discharge, having at least one first diode coupled between the supply node and the output terminal. A cut-off electronic lock couples, in the inactive state, the supply node to the supply terminal by reverse biasing the at least one first diode to make a voltage of the output terminal float.

Abstract: An arithmetic-logic unit for a digital signal processor, processing audio signals, having a multiplier circuit able to receive in input a first and a second signal and to supply in output a third signal which represents the result of the multiplication of said first and second signal, a generator circuit of a dither signal, a summation circuit downline of the multiplier circuit, said summation circuit being able to perform an addition operation between said third signal and the dither signal so as to supply a fourth signal in output, and a truncation or rounding circuit downline of the summation circuit, able to truncate or round said fourth signal.

Abstract: An electric circuit includes a supply terminal to receive an outer supply voltage and a voltage regulator coupled to the supply terminal and to provide supply and resting voltages. A lock-out circuit is switchable between active and inactive states and receives the supply voltage at a supply node to generate, in the active state, an output voltage on a output terminal thereof. A protection circuit protects against electrostatic discharge, having at least one first diode coupled between the supply node and the output terminal. A cut-off electronic lock couples, in the inactive state, the supply node to the supply terminal by reverse biasing the at least one first diode to make a voltage of the output terminal float.

Abstract: A single-ended or differential single-stage, or multi-stage sigma-delta analog-to-digital converter includes at least one switched-capacitor integrator comprising a switched-capacitor network receiving as input a signal to be sampled, and an amplifier coupled in cascade to the switched-capacitor network. A circuit is coupled to the amplifier for feeding an analog dither signal to a virtual ground of the amplifier.

Abstract: A single-ended or differential single-stage, or multi-stage sigma-delta analog-to-digital converter includes at least one switched-capacitor integrator comprising a switched-capacitor network receiving as input a signal to be sampled, and an amplifier coupled in cascade to the switched-capacitor network. A circuit is coupled to the amplifier for feeding an analog dither signal to a virtual ground of the amplifier.

Abstract: A boosted sampling circuit that is relatively straightforward to form is provided, as well as a corresponding method for driving the same. The input voltage applied to the boosted sampling circuit may be equal to a supply voltage or may be greater than a maximum voltage level allowed by the prior art circuits. This result is attained by connecting the control nodes of a plurality of switches to the input node while a first control phase is active, and by connecting a current terminal of another switch to a biasing voltage for protecting it from breakdowns.

Abstract: A boosted sampling circuit that is relatively straightforward to form is provided, as well as a corresponding method for driving the same. The input voltage applied to the boosted sampling circuit may be equal to a supply voltage or may be greater than a maximum voltage level allowed by the prior art circuits. This result is attained by connecting the control nodes of a plurality of switches to the input node while a first control phase is active, and by connecting a current terminal of another switch to a biasing voltage for protecting it from breakdowns.

Abstract: The boosted switch device comprises an input terminal and an output terminal; a supply line set to a supply potential; a ground line set to a ground potential; a transistor connected between the input and output terminals; a capacitor; and a switch device connecting the capacitor between the supply line and the ground line, when the transistor is off, and between the input terminal and the control terminal of the transistor, when the transistor is on.

Abstract: A digital decimation filter includes a set of cascaded integrator stages for generating a first signal comprised of bit words including a first number of bits as well as a set of cascaded derivative stages for receiving said first signal and generating therefrom an output comprised of bit words including a second number of bits. The second number of bits is smaller than said first number of bits and a bit discarding unit is located downstream of the integrator stages and upstream of the derivative stages for discarding a given number of least significant bits from the bit words of the first signal before this is received by the derivative stages. Said given number is defined as the difference between said first and said second number of bits.

Abstract: The present invention refers to a digital to analog conversion circuit able to transform an input digital signal having n bit in a signal having a thermometric code and to convert it in an analog output signal.

Abstract: The present invention refers to a digital to analog conversion circuit able to transform an input digital signal having n bit in a signal having a thermometric code and to convert it in an analog output signal.

Abstract: The boosted switch device comprises an input terminal and an output terminal; a supply line set to a supply potential; a ground line set to a ground potential; a transistor connected between the input and output terminals; a capacitor; and a switch device connecting the capacitor between the supply line and the ground line, when the transistor is off, and between the input terminal and the control terminal of the transistor, when the transistor is on.