Patents by Inventor Carlos A. Gonzalez

Carlos A. Gonzalez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10804637
    Abstract: A connector-assembly includes a connector-housing and a primary-lock-reinforcement device. The connector-housing retains electrical-terminals within terminal-cavities defined by a terminal-tower disposed within the connector-housing. The electrical-terminals mate with one or more corresponding electrical-terminals along a mating-axis of the connector-assembly. The primary-lock-reinforcement device slideably engages the terminal-tower and is moveable from a shipping-position to a pre-stage-position. The primary-lock-reinforcement device has a base and a skirt. The primary-lock-reinforcement device has a post extending beyond an inner-surface of the skirt that engages a corresponding L-shaped slot defined by an outer-surface of the terminal-tower. The corresponding L-shaped slot has a first-leg and a second-leg. The first-leg defines a wall configured to inhibit a movement of the primary-lock-reinforcement device along the mating-axis.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: October 13, 2020
    Assignee: APTIV TECHNOLOGIES LIMITED
    Inventors: Carlos A. Gonzalez Delgadillo, Jorge I. Escamilla Rodriguez, Pedro Yabur Pacheco
  • Patent number: 10622755
    Abstract: A connector assembly includes a mat seal and a conductor seal. The mat seal is shaped to fit within an opening in a connector housing of the connector assembly. The mat seal defines at least one a seal passage extending therethrough. The conductor seal defines a conductor passage extending therethrough. The conductor seal is configured to receive conductor, such as an insulated electrical cable, within the conductor passage. The conductor seal is received within the seal passage. The mat seal and the conductor seal cooperate to inhibit intrusion of contaminants into the connector housing. A method of assembling a connector assembly having a mat seal and a conductor seal is also presented herein.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: April 14, 2020
    Assignee: Aptiv Technologies Limited
    Inventors: Carlos A. Gonzalez Delgadillo, Jorge I. Escamilla Rodriguez, Pedro Yabur Pacheco
  • Publication number: 20200083631
    Abstract: A connector-assembly includes a connector-housing and a primary-lock-reinforcement device. The connector-housing retains electrical-terminals within terminal-cavities defined by a terminal-tower disposed within the connector-housing. The electrical-terminals mate with one or more corresponding electrical-terminals along a mating-axis of the connector-assembly. The primary-lock-reinforcement device slideably engages the terminal-tower and is moveable from a shipping-position to a pre-stage-position. The primary-lock-reinforcement device has a base and a skirt. The primary-lock-reinforcement device has a post extending beyond an inner-surface of the skirt that engages a corresponding L-shaped slot defined by an outer-surface of the terminal-tower. The corresponding L-shaped slot has a first-leg and a second-leg. The first-leg defines a wall configured to inhibit a movement of the primary-lock-reinforcement device along the mating-axis.
    Type: Application
    Filed: July 30, 2019
    Publication date: March 12, 2020
    Inventors: Carlos A. Gonzalez Delgadillo, Jorge I. Escamilla Rodriguez, Pedro Yabur Pacheco
  • Patent number: 10418742
    Abstract: A connector-assembly includes a connector-housing and a primary-lock-reinforcement device. The connector-housing retains electrical-terminals within terminal-cavities defined by a terminal-tower disposed within the connector-housing. The electrical-terminals mate with one or more corresponding electrical-terminals along a mating-axis of the connector-assembly. The primary-lock-reinforcement device slideably engages the terminal-tower and is moveable from a shipping-position to a pre-stage-position. The primary-lock-reinforcement device has a base and a skirt. The primary-lock-reinforcement device has a post extending beyond an inner-surface of the skirt that engages a corresponding L-shaped slot defined by an outer-surface of the terminal-tower. The corresponding L-shaped slot has a first-leg and a second-leg. The first-leg defines a wall configured to inhibit a movement of the primary-lock-reinforcement device along the mating-axis.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: September 17, 2019
    Assignee: DELPHI TECHNOLOGIES, LLC
    Inventors: Carlos A. Gonzalez Delgadillo, Jorge I. Escamilla Rodriguez, Pedro Yabur Pacheco
  • Patent number: 7498678
    Abstract: High yield, high reliability, flip-chip integrated circuit (IC) packages are achieved utilizing a combination of heat and pressure to bond flip-chip die and to cure no-flow underfill material. The underfill comprises a filler or low coefficient of thermal expansion (CTE) material to decrease CTE of the cured underfill. The filler material can be selected from the group comprising silica, silicon oxide, silicon dioxide, silicon nitride, aluminum oxide, aluminum nitride, or a mixture thereof. The filler material may also increase the viscosity of the uncured underfill and/or increase the modulus of elasticity of the cured underfill. In some method embodiments, a thermocompression bonder is used to simultaneously provide solder bump reflow and underfill curing. Application of various methods to a component package, an electronic assembly, and an electronic system are also described.
    Type: Grant
    Filed: August 16, 2007
    Date of Patent: March 3, 2009
    Assignee: Intel Corporation
    Inventors: Carlos A. Gonzalez, Song-Hua Shi, Milan Djukic
  • Patent number: 7323360
    Abstract: High yield, high reliability, flip-chip integrated circuit (IC) packages are achieved utilizing a combination of heat and pressure to bond flip-chip die and to cure no-flow underfill material. The underfill comprises a filler or low coefficient of thermal expansion (CTE) material to decrease CTE of the cured underfill. The filler material can be selected from the group comprising silica, silicon oxide, silicon dioxide, silicon nitride, aluminum oxide, aluminum nitride, or a mixture thereof. The filler material may also increase the viscosity of the uncured underfill and/or increase the modulus of elasticity of the cured underfill. In some method embodiments, a thermocompression bonder is used to simultaneously provide solder bump reflow and underfill curing. Application of various methods to a component package, an electronic assembly, and an electronic system are also described.
    Type: Grant
    Filed: October 26, 2001
    Date of Patent: January 29, 2008
    Assignee: Intel Corporation
    Inventors: Carlos A. Gonzalez, Song-Hua Shi, Milan Djukic
  • Patent number: 7235886
    Abstract: A chip-join process to reduce elongation mismatch between the adherents involves thermally expanding each of a coefficient of thermal expansion mismatched semiconductor chip and substrate a substantially equal amount from their room temperature state in a direction along surfaces thereof to be joined by soldering. The thermally expanded semiconductor chip and substrate are then soldered to one another forming a plurality of soldered joints, and then cooled to room temperature. The process enables elongation mismatch from soldering to be reduced to less than half that expected based up cooling the substrate and semiconductor chip from the solder solidification temperature following soldering, thereby reducing post soldering residual stress, residual plastic deformation in the soldered joints, residual plastic deformation in the substrate, and semiconductor chip warpage.
    Type: Grant
    Filed: December 21, 2001
    Date of Patent: June 26, 2007
    Assignee: Intel Corporation
    Inventors: Biju Chandran, Carlos A. Gonzalez
  • Patent number: 7122403
    Abstract: A low resistance package-to-die interconnect scheme for reduced die stresses includes a relatively low melting temperature and yield strength solder on the die and a relatively higher melting temperature and electrically conductive material such as copper on the substrate. A soldered joint connects the solder to the electrically conductive material to couple/connect the die and substrate to one another. The soldered joint is formed by heating the die and solder thereon to at least the melting temperature of the solder and thereafter contacting the molten solder with the conductive material on the substrate, which is at a substantially lower temperature for minimizing residual stress from soldering due to coefficient of thermal expansion mismatch between the substrate and die.
    Type: Grant
    Filed: December 10, 2004
    Date of Patent: October 17, 2006
    Assignee: Intel Corporation
    Inventors: Biju Chandran, Carlos A. Gonzalez
  • Patent number: 7096580
    Abstract: A thin, lightweight retention mechanism with a spring force holds an integrated circuit package to a circuit board. The retention mechanism consists of a pressure plate, a backing plate, and a fastening means for applying a deforming force to the plates, such as screws and nuts. The plates are paraboloid or dish-shaped and made of an elastically deformable material, such as steel. The fastening means simultaneously applies deforming forces to the peripheries of the plates to create a continuous spring force to effect electrical continuity between the integrated circuit package and the circuit board. In addition, a method of testing the retention mechanism and a method of assembling the retention mechanism are disclosed.
    Type: Grant
    Filed: March 22, 2005
    Date of Patent: August 29, 2006
    Assignee: Intel Corporation
    Inventors: Carlos A. Gonzalez, Leo Ofman
  • Patent number: 6884943
    Abstract: A thin, lightweight retention mechanism with a spring force holds an integrated circuit package to a circuit board. The retention mechanism consists of a pressure plate, a backing plate, and a fastening means for applying a deforming force to the plates, such as screws and nuts. The plates are paraboloid or dish-shaped and made of an elastically deformable material, such as steel. The fastening means simultaneously applies deforming forces to the peripheries of the plates to create a continuous spring force to effect electrical continuity between the integrated circuit package and the circuit board. In addition, a method of testing the retention mechanism and a method of assembling the retention mechanism are disclosed.
    Type: Grant
    Filed: August 4, 2003
    Date of Patent: April 26, 2005
    Assignee: Intel Corporation
    Inventors: Carlos A. Gonzalez, Leo Ofman
  • Patent number: 6752634
    Abstract: An array of contacts for electrically connecting a semiconductor package to a circuit board. The contacts are carried by a tape having an adhesive border. The tape, along with the contacts, are applied easily to either the substrate or the circuit board using the adhesive border. Each contact is made of two S-shaped pieces in perpendicular directions. The contacts are inserted into holes in the tape and held there by friction.
    Type: Grant
    Filed: September 21, 2001
    Date of Patent: June 22, 2004
    Assignee: Intel Corporation
    Inventors: Carlos A. Gonzalez, Biju Chandran
  • Patent number: 6750551
    Abstract: A surface mount-type microelectronic component assembly which does not physically attach the microelectronic component to its carrier substrate. Electrical contact is achieved between the microelectronic component and the carrier with solder balls attached to either the microelectronic component or the carrier substrate. A force is exerted on the assembly to achieve sufficient electrical contact between the microelectronic component and the carrier substrate.
    Type: Grant
    Filed: December 28, 1999
    Date of Patent: June 15, 2004
    Assignee: Intel Corporation
    Inventors: Kristopher Frutschy, Charles A. Gealer, Carlos A. Gonzalez
  • Patent number: 6750549
    Abstract: A ball grid array device includes a substrate and a die attached to the substrate. The substrate further includes a first major surface and a second major surface. A first ball, having an attached end and a distal tip end, is attached to a major surface of the substrate. The first ball has a first height. A second ball, having an attached end and a distal tip end, is also attached to the major surface. The second ball has a second height different from the first height. The first height and the second height are selected to produce a substantially co-planar surface at the distal tip ends of the first ball and the second ball. The major surface is not substantially co-planar. A method for forming the balls of a ball grid array device on a major of a substrate includes determining height differences across the major surface of the substrate, placing lands on the substrate, and forming a plurality of balls on the lands. Each of the balls has an attached portion and a tip portion.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: June 15, 2004
    Assignee: Intel Corporation
    Inventors: Biju I. Chandran, Carlos A. Gonzalez
  • Patent number: 6672892
    Abstract: A retention module includes a socket to connect to a package. At least one retention arm is coupled to the socket. The at least one retention arm extends perpendicular to the socket. At least one retention clamp is coupled to the at least one retention arm to secure placement of a heat sink against a surface of a package assembly.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: January 6, 2004
    Assignee: Intel Corporation
    Inventors: Biju Chandran, Carlos A. Gonzalez
  • Patent number: 6657131
    Abstract: A thin, lightweight retention mechanism with a spring force holds an integrated circuit package to a circuit board. The retention mechanism consists of a pressure plate, a backing plate, and a fastening means for applying a deforming force to the plates, such as screws and nuts. The plates are paraboloid or dish-shaped and made of an elastically deformable material, such as steel. The fastening means simultaneously applies deforming forces to the peripheries of the plates to create a continuous spring force to effect electrical continuity between the integrated circuit package and the circuit board. In addition, a method of testing the retention mechanism and a method of assembling the retention mechanism are disclosed.
    Type: Grant
    Filed: December 8, 2000
    Date of Patent: December 2, 2003
    Assignee: Intel Corporation
    Inventors: Carlos A. Gonzalez, Leo Ofman
  • Patent number: 6600652
    Abstract: A retention module includes a socket to connect to a package. At least one retention arm is coupled to the socket. At least one clamping bar is coupled to the at least one retention arm to secure placement of a heat sink against a surface of a package assembly.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: July 29, 2003
    Assignee: Intel Corporation
    Inventors: Biju Chandran, Carlos A. Gonzalez
  • Publication number: 20030116860
    Abstract: A low resistance package-to-die interconnect scheme for reduced die stresses includes a relatively low melting temperature and yield strength solder on the die and a relatively higher melting temperature and electrically conductive material such as copper on the substrate. A soldered joint connects the solder to the electrically conductive material to couple/connect the die and substrate to one another. The soldered joint is formed by heating the die and solder thereon to at least the melting temperature of the solder and thereafter contacting the molten solder with the conductive material on the substrate, which is at a substantially lower temperature for minimizing residual stress from soldering due to coefficient of thermal expansion mismatch between the substrate and die.
    Type: Application
    Filed: December 21, 2001
    Publication date: June 26, 2003
    Inventors: Biju Chandran, Carlos A. Gonzalez
  • Publication number: 20030080437
    Abstract: High yield, high reliability, flip-chip integrated circuit (IC) packages are achieved utilizing a combination of heat and pressure to bond flip-chip die and to cure no-flow underfill material. The underfill comprises a filler or low coefficient of thermal expansion (CTE) material to decrease CTE of the cured underfill. The filler material can be selected from the group comprising silica, silicon oxide, silicon dioxide, silicon nitride, aluminum oxide, aluminum nitride, or a mixture thereof. The filler material may also increase the viscosity of the uncured underfill and/or increase the modulus of elasticity of the cured underfill. In some method embodiments, a thermocompression bonder is used to simultaneously provide solder bump reflow and underfill curing. Application of various methods to a component package, an electronic assembly, and an electronic system are also described.
    Type: Application
    Filed: October 26, 2001
    Publication date: May 1, 2003
    Applicant: Intel Corporation
    Inventors: Carlos A. Gonzalez, Song-Hua Shi, Milan Djukic
  • Publication number: 20030063440
    Abstract: A retention module includes a socket to connect to a package. At least one retention arm is coupled to the socket. At least one clamping bar is coupled to the at least one retention arm to secure placement of a heat sink against a surface of a package assembly.
    Type: Application
    Filed: September 28, 2001
    Publication date: April 3, 2003
    Inventors: Biju Chandran, Carlos A. Gonzalez
  • Publication number: 20030064618
    Abstract: A retention module includes a socket to connect to a package. At least one retention arm is coupled to the socket. The at least one retention arm extends perpendicular to the socket. At least one retention clamp is coupled to the at least one retention arm to secure placement of a heat sink against a surface of a package assembly.
    Type: Application
    Filed: September 28, 2001
    Publication date: April 3, 2003
    Inventors: Biju Chandran, Carlos A. Gonzalez