Abstract: An integrated circuit fabrication process includes a selective substrate implant process to effectively decouple a first power supply connection from a second power supply connection while providing immunity against parasitic effects. In one embodiment, the selective substrate implant process forms heavily doped p-type regions only under P-wells in which noise producing circuitry are built. The noisy ground connection for these P-wells are decoupled from the quiet ground connection for others P-wells not connected to any heavily doped regions and in which noise sensitive circuitry are built. The selective substrate implant process of the present invention has particular applications in forming CMOS analog integrated circuits where it is important to decouple the analog ground for sensitive analog circuitry from the often noisy digital grounds of the digital and power switching circuitry.

Abstract: An operational amplifier having an input and an output stage. The input stage includes first and second source-coupled NMOS input transistors for accepting a differential input voltage and first and second PMOS load transistors for supplying current to each input transistor. A node between the first input transistor and first load transistor is coupled to a gate of a third PMOS transistor having its source coupled to a positive supply and its drain coupled to the sources of the input transistors and to a negative supply through a first biasing transistor. The output stage includes a fourth PMOS transistor having its gate coupled to a node between the second input transistor and the second load transistor and a source coupled to the positive supply voltage. A drain of the output transistor forms an output node and is coupled to the negative supply through a second biasing transistor.