Abstract: Circuits and methods providing a electronic power supply applicable to any dual supply rail systems, which require a smooth and uninterrupted output supply and a replica power path and autonomous mode of operation from the system power supply are disclosed. In a preferred embodiment of the invention the power supply is applied to a real time clock. An Innovative Replica Power Path concept and circuit implementation ensures the smooth and uninterrupted transfer of power from one input source to the other. The circuit features a Latched Supply Comparator that guarantees the commutation to the Replica Power Path only happens after the voltage is settled. Zero power consumption from the back-up energy source is achieved in the presence of an alternative higher voltage source. The generated RTC supply voltage does not suffer from abrupt changes when the voltage level of the main system power source (battery or charger) is connected or disconnected.

Abstract: Method and circuits enable measuring output current in DC/DC converters operating in pulse frequency modulation (PFM) mode and in pulse width modulation (PWM) mode. The method is applicable to DC/DC converters using an inductor at the output. Current is sampled on one pass transistor only. The DC/DC converter disclosed turns a PMOS transistor off when the output current reaches its current limit.

Abstract: Method and circuits enable measuring output current in DC/DC converters operating in pulse frequency modulation (PFM) mode and in pulse width modulation (PWM) mode. The method is applicable to DC/DC converters using an inductor at the output. Current is sampled on one pass transistor only. The DC/DC converter disclosed turns a PMOS transistor off when the output current reaches its current limit.

Abstract: Circuits and methods providing a electronic power supply applicable to any dual supply rail systems, which require a smooth and uninterrupted output supply and a replica power path and autonomous mode of operation from the system power supply are disclosed. In a preferred embodiment of the invention the power supply is applied to a real time clock. An Innovative Replica Power Path concept and circuit implementation ensures the smooth and uninterrupted transfer of power from one input source to the other. The circuit features a Latched Supply Comparator that guarantees the commutation to the Replica Power Path only happens after the voltage is settled. Zero power consumption from the back-up energy source is achieved in the presence of an alternative higher voltage source. The generated RTC supply voltage does not suffer from abrupt changes when the voltage level of the main system power source (battery or charger) is connected or disconnected.

Abstract: Circuits and methods providing a electronic power supply applicable to any dual supply rail systems, which require a smooth and uninterrupted output supply and a replica power path and autonomous mode of operation from the system power supply are disclosed. In a preferred embodiment of the invention the power supply is applied to a real time clock. An Innovative Replica Power Path concept and circuit implementation ensures the smooth and uninterrupted transfer of power from one input source to the other. The circuit features a Latched Supply Comparator that guarantees the commutation to the Replica Power Path only happens after the voltage is settled. Zero power consumption from the back-up energy source is achieved in the presence of an alternative higher voltage source. The generated RTC supply voltage does not suffer from abrupt changes when the voltage level of the main system power source (battery or charger) is connected or disconnected.

Abstract: A self-biased reference circuit device (100) includes a first cascode current mirror (116), a second cascode current mirror (118), and a startup circuit (108). The first cascode current mirror (116) is capable to generate a first bias voltage (136) and a second bias voltage (140) in response to a first current and to generate a second current in response to the first and second bias voltages. The second cascode current mirror (118) is capable to generate a third bias voltage (164) in response to the second current, to generate a fourth bias voltage (168) in response to a third current, and to generate the first current in response to the third and fourth bias voltages. The startup circuit includes a first switch (188) and a second switch (196). The first switch (188) is capable to connect the first bias voltage (136) and fourth bias voltage (168) during startup.

Abstract: Circuits and methods for power efficient generation of supply voltages and currents in an integrated circuit by reducing the power consumption of all core analog circuit blocks by a pulsed operation mode are disclosed. In a preferred embodiment of the invention the invention has been applied to a power management chip. Pulsed Mode of Operation of ALL core analog blocks—internal LDO/s, VREF an IBIAS generators, results in significantly reduced power consumption. New circuit realizations and control algorithms to improve the ON/OFF ratio of the Pulsed Mode Operation yield in better power efficiency. Innovative circuit implementation consisting of an additional Top Up Buffer Amplifier stage ensures a fast recharge of VREF output, thus allowing shorter ON times and respectively even better power efficiency. Bypassing a low bandwidth and slow to start LDO with a fast Bypass Comparator supplies a LDO rail in Pulsed Mode of operation.

Abstract: Circuits and methods providing a electronic power supply applicable to any dual supply rail systems, which require a smooth and uninterrupted output supply and a replica power path and autonomous mode of operation from the system power supply are disclosed. In a preferred embodiment of the invention the power supply is applied to a real time clock. An Innovative Replica Power Path concept and circuit implementation ensures the smooth and uninterrupted transfer of power from one input source to the other. The circuit features a Latched Supply Comparator that guarantees the commutation to the Replica Power Path only happens after the voltage is settled. Zero power consumption from the back-up energy source is achieved in the presence of an alternative higher voltage source. The generated RTC supply voltage does not suffer from abrupt changes when the voltage level of the main system power source (battery or charger) is connected or disconnected.

Abstract: A self-biased reference circuit device (100) includes a first cascode current mirror (116), a second cascode current mirror (118), and a startup circuit (108). The first cascode current mirror (116) is capable to generate a first bias voltage (136) and a second bias voltage (140) in response to a first current and to generate a second current in response to the first and second bias voltages. The second cascode current mirror (118) is capable to generate a third bias voltage (164) in response to the second current, to generate a fourth bias voltage (168) in response to a third current, and to generate the first current in response to the third and fourth bias voltages. The startup circuit includes a first switch (188) and a second switch (196). The first switch (188) is capable to connect the first bias voltage (136) and fourth bias voltage (168) during startup.

Abstract: Circuits and methods for power efficient generation of supply voltages and currents in an integrated circuit by reducing the power consumption of all core analog circuit blocks by a pulsed operation mode are disclosed. In a preferred embodiment of the invention the invention has been applied to a power management chip. Pulsed Mode of Operation of ALL core analog blocks—internal LDO/s, VREF an IBIAS generators, results in significantly reduced power consumption. New circuit realizations and control algorithms to improve the ON/OFF ratio of the Pulsed Mode Operation yield in better power efficiency. Innovative circuit implementation consisting of an additional Top Up Buffer Amplifier stage ensures a fast recharge of VREF output, thus allowing shorter ON times and respectively even better power efficiency. Bypassing a low bandwidth and slow to start LDO with a fast Bypass Comparator supplies a LDO rail in Pulsed Mode of operation.