Patents by Inventor Carlos Eduardo Lozoya Lopez

Carlos Eduardo Lozoya Lopez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10812075
    Abstract: An apparatus includes a terminal, a first device coupled to the terminal via a first node, the first device to drive a signal on the terminal via the first node, and a second device coupled to the terminal via a second node, wherein the second device comprises a dynamic on-die termination (ODT) circuit coupled to the second node. The dynamic ODT circuit includes: a bus holder circuit to receive the signal from the first device at the second node and select a termination voltage based on the signal, a response delay circuit coupled to the bus holder circuit, the response delay circuit to delay application of the termination voltage to the second node, and a time blanking delay circuit coupled to the bus holder circuit and the response delay circuit to prevent the termination voltage from changing before a threshold period of time elapses.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: October 20, 2020
    Assignee: Intel Corporation
    Inventors: Harry Muljono, Linda K. Sun, Maria Jose Garcia Garcia de Leon, Raul Enriquez Shibayama, Abraham Isidoro Munoz, Carlos Eduardo Lozoya Lopez
  • Publication number: 20190280691
    Abstract: An apparatus includes a terminal, a first device coupled to the terminal via a first node, the first device to drive a signal on the terminal via the first node, and a second device coupled to the terminal via a second node, wherein the second device comprises a dynamic on-die termination (ODT) circuit coupled to the second node. The dynamic ODT circuit includes: a bus holder circuit to receive the signal from the first device at the second node and select a termination voltage based on the signal, a response delay circuit coupled to the bus holder circuit, the response delay circuit to delay application of the termination voltage to the second node, and a time blanking delay circuit coupled to the bus holder circuit and the response delay circuit to prevent the termination voltage from changing before a threshold period of time elapses.
    Type: Application
    Filed: May 20, 2019
    Publication date: September 12, 2019
    Applicant: Intel Corporation
    Inventors: Harry Muljono, Linda K. Sun, Maria Jose Garcia Garcia de Leon, Raul Enriquez Shibayama, Abraham Isidoro Munoz, Carlos Eduardo Lozoya Lopez