Patents by Inventor Carlos Esteban Muñoz

Carlos Esteban Muñoz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Systems and methods for adaptive auto-calibration of Radix<2 A/D SAR converters with internally generated stimuli
    Patent number: 6486806
    Abstract: An auto-calibrating companion bit successive approximation system uses sampling and balancing capacitors in a charge redistribution digital-to-analog converter having multi-valued capacitors of magnitudes enabling redundant expression of electric charge values. Companion bits are used with sets of balancing capacitors for successive approximation of sampling voltages. A charge redistribution digital-to-analog converter has a sampling and balancing capacitors including associated companion bit capacitors represented by digital weights which are saved in memory. A non-binary weighted set of capacitors provides redundancy in a charge redistribution digital-to-analog converter employed in a successive approximation register architecture.
    Type: Grant
    Filed: September 9, 1999
    Date of Patent: November 26, 2002
    Assignee: Cirrus Logic, Inc.
    Inventors: Carlos Esteban Muñoz, Karl Ernesto Thompson, Douglas S. Piasecki, Wai Laing Lee, Eric Swanson
  • Successive approximation algorithm-based architectures and systems
    Patent number: 6424276
    Abstract: A digital calibration system for an analog-to-digital converter system includes a computational system receiving digital bits from an analog-to-digital converter representing selection of elements of the digital-to-analog converter in response to an analog input. The computational engine produces a digital output representative of the analog input during conversion operation, and digital values for adjustment of an adjustable analog source during calibration. Further, a digital system comprises a radix-less-than-two non-configurable digital-to-analog converter, a comparator system connected to the converter, and a computational system configured for SAR calibration and conversion.
    Type: Grant
    Filed: September 9, 1999
    Date of Patent: July 23, 2002
    Assignee: Cirrus Logic, Inc.
    Inventors: Carlos Esteban Muñoz, Karl Ernesto Thompson, Douglas S. Piasecki, Wai Laing Lee, Eric Swanson
  • System and apparatus for digitally calibrating capacitors in an analog-to-digital converter using successive approximation
    Patent number: 6417794
    Abstract: A digital calibration system for an analog-to-digital converter system includes a computational system receiving digital bits from an analog-to-digital converter representing selection of elements of the digital-to-analog converter in response to an analog input. The computational engine produces a digital output representative of the analog input during conversion operation, and digital values for adjustment of an adjustable analog source during calibration. Further, a digital system comprises a radix-less-than-two non-configurable digital-to-analog converter, a comparator system connected to the converter, and a computational system configured for SAR calibration and conversion.
    Type: Grant
    Filed: September 9, 1999
    Date of Patent: July 9, 2002
    Assignee: Cirrus Logic, Inc.
    Inventors: Carlos Esteban Muñoz, Karl Ernesto Thompson, Douglas S. Piasecki, Wai Laing Lee, Eric Swanson
  • System and method of selecting and using bit testing sequences during successive approximation for calibrating an analog-to-digital converter
    Patent number: 6404375
    Abstract: A digital calibration system for an analog-to-digital converter system includes a computational system receiving digital bits from an analog-to-digital converter representing selection of elements of the digital-to-analog converter in response to an analog input. The computational engine produces a digital output representative of the analog input during conversion operation, and digital values for adjustment of an adjustable analog source during calibration. Further, a digital system comprises a radix-less-than-two non-configurable digital-to-analog converter, a comparator system connected to the converter, and a computational system configured for SAR calibration and conversion.
    Type: Grant
    Filed: September 9, 1999
    Date of Patent: June 11, 2002
    Assignee: Cirrus Logic, Inc.
    Inventors: Carlos Esteban Muñoz, Karl Ernesto Thompson, Douglas S. Piasecki, Wai Laing Lee, Eric Swanson
  • Calibrated quasi-autozeroed comparator systems and methods
    Patent number: 6252454
    Abstract: A multistage comparator is calibrated to remove quasi-autozero voltages derived from the native comparator offset and autozero switch charge injection offsets. A multistage comparator includes a plurality of series connected amplifiers each having a programmable source, and further including a latch. A calibration method for a multistage comparator includes calibrating the first of a series of amplifiers first for both voltage offset and charge injection errors thereby to remove the quasi-autozero voltage and charge injection offsets.
    Type: Grant
    Filed: September 9, 1999
    Date of Patent: June 26, 2001
    Assignee: Cirrus Logic, Inc.
    Inventors: Karl Ernesto Thompson, Carlos Esteban Muñoz, Douglas S. Piasecki, Wai Laing Lee, Eric Swanson