Abstract: A memory (10) has a plurality of memory cells, a serial address port (47) for receiving a low voltage high frequency differential address signal, and a serial input/output data port (52, 54) for receiving a high frequency low voltage differential data signal. The memory (10) can operate in one of two different modes, a normal mode and a cache line mode. In cache line mode, the memory can access an entire cache line from a single address. A fully hidden refresh mode allows for timely refresh operations while operating in cache line mode. Data is stored in the memory array (14) by interleaving in multiple sub-arrays (15, 17). During a hidden refresh mode of operation, one sub-array (15) is accessed while another sub-array (17) is refreshed. Two or more of the memories (10) may be chained together to provide a high speed low power memory system.

Abstract: A level shifter circuit including first and second circuits and a protection layer. The first circuit receives an input signal and switches first and second nodes to opposite states within a first voltage range between first and second supply voltages. The second circuit switches the third and fourth nodes to opposite states within a second voltage range between third and fourth supply voltages in response to switching of the first and second nodes. The protection layer couples the first and second nodes to third and fourth nodes via respective first and second isolation paths. The isolation paths operate to keep the first and second nodes within the first voltage range and to keep the third and fourth nodes within the second voltage range. Isolation enables the use of thin gate-oxide devices for speed while extending the voltage range beyond the maximum voltage allowable for a single thin gate-oxide device.

Abstract: A high speed output buffer including an input circuit providing first and second signals within a first voltage range having a first common mode voltage, an AC interface receiving the first and second signals and providing first and second preliminary drive signals, a detection and correction circuit that corrects a state of the first preliminary drive signal AC coupled to the first signal, first and second drive circuits receiving the preliminary drive signals and providing first and second drive signals, where the first drive circuit operates within a second voltage range having a greater common mode voltage and where the second drive circuit operates within a third voltage range, and an output that switches an output node within a voltage range that is greater than a maximum voltage range. The first, second and third voltage ranges are each within the maximum voltage range suitable for thin-gate devices.

Abstract: A programmable PLL including a receiver, a phase frequency detector, a charge pump, and a VCO. The receiver includes a programmable capacitor voltage divider that shifts voltage of an input clock to provide a level-shifted clock. The AC interface includes a state detection and correction circuit that ensures proper state of the level-shifted clock. The PLL includes a pulse delay modulator for generating delayed clock control signals. The VCO includes a programmable phase control circuit that dynamically adjusts phase using the delayed clock control signals. The VCO circuit includes a ring oscillator circuit with one or more phase control nodes. The programmable phase control circuit selectively couples devices to the phase control node using the clock control signals to adjust phase. The devices may be capacitors or transistors, each switched using switches controlled by the delayed clock control signals. The capacitors may be metal capacitors or semiconductor transistor capacitors.

Abstract: A memory (10) has a plurality of memory cells, a serial address port (47) for receiving a low voltage high frequency differential address signal, and a serial input/output data port (52, 54) for receiving a high frequency low voltage differential data signal. The memory (10) can operate in one of two different modes, a normal mode and a cache line mode. In cache line mode, the memory can access an entire cache line from a single address. A fully hidden refresh mode allows for timely refresh operations while operating in cache line mode. Data is stored in the memory array (14) by interleaving in multiple sub-arrays (15, 17). During a hidden refresh mode of operation, one sub-array (15) is accessed while another sub-array (17) is refreshed. Two or more of the memories (10) may be chained together to provide a high speed low power memory system.

Abstract: Hashing and pattern matching are used in an information processing system to process incoming messages from a network such as an Ethernet-based network. Using hashing and pattern matching increases the efficiency of message acceptance and rejection without increasing software-based processor tasks. A hash function and a pattern matching function are performed on a message received by an information processing system, and the message is selectively accepted based on at least one of a hash result and a pattern matching result. The incoming message can be searched for the existence of patterns and the absence of the patterns. The incoming message can be searched for the existence of multiple patterns. The results of pattern matching can be used not only for acceptance and rejection of messages, but also for other post-receipt tasks such as selective storage of incoming messages according to identified relative priorities or absolute criticality of messages having particular pattern matches.

Abstract: Hashing and pattern matching are used in an information processing system to process incoming messages from a network such as an Ethernet-based network. Using hashing and pattern matching increases the efficiency of message acceptance and rejection without increasing software-based processor tasks. A hash function and a pattern matching function are performed on a message received by an information processing system, and the message is selectively accepted based on at least one of a hash result and a pattern matching result. The incoming message can be searched for the existence of patterns and the absence of the patterns. The incoming message can be searched for the existence of multiple patterns. The results of pattern matching can be used not only for acceptance and rejection of messages, but also for other post-receipt tasks such as selective storage of incoming messages according to identified relative priorities or absolute criticality of messages having particular pattern matches.