Abstract: An active terminator is configured with switches to select between terminating two lines for transmitting one differential signal pair or two single ended signals terminated in a pseudo-differential receiver. The receiver circuitry is configured with three differential comparators. One differential comparator receives both signal lines and other two differential comparators each receive one signal line and a reference voltage. The signal lines are terminated in a resistive voltage divider with electronic switches coupling the positive and ground voltages. The top and bottom nodes of the resistor divider in both terminators are cross-coupled with pass gates. In the pseudo-differential mode the pass gates are OFF and the electronic switches are ON with known resistances. In the differential mode, the electronic switches are OFF and the pass gates are ON with known resistances. The pass gate and switch resistances are sized with the resistors to insure a desired termination impedance.

Abstract: An active terminator is configured with switches to select between terminating two lines for transmitting one differential signal pair or two single ended signals terminated in a pseudo-differential receiver. The receiver circuitry is configured with three differential comparators. One differential comparator receives both signal lines and other two differential comparators each receive one signal line and a reference voltage. The signal lines are terminated in a resistive voltage divider with electronic switches coupling the positive and ground voltages. The top and bottom nodes of the resistor divider in both terminators are cross-coupled with pass gates. In the pseudo-differential mode the pass gates are OFF and the electronic switches are ON with known resistances. In the differential mode, the electronic switches are OFF and the pass gates are ON with known resistances. The pass gate and switch resistances are sized with the resistors to insure a desired termination impedance.

Abstract: Rapid switching is provided by a circuit that controls the current passing through a chain of CMOS devices arranged in a series circuit. A node output terminal to the circuit is provided intermediate the chain to control the partially conductive state of two other CMOS devices. Voltages at the output terminal sets one or the other of the two CMOS devices in the current conducting state. That state is a partially conducting state of the CMOS device so that small changes flowing in the current path allows a quick transfer of the operating state to the other device. With this arrangement, discharging of large capacitances is avoided by using the small current changes to rapidly switch between the partially conducting CMOS devices.