Abstract: The idea of the invention is to coat the free surface of patterned Cu conducting lines in on-chip interconnections (BEOL) wiring by a 1-20 nm thick metal layer prior to deposition of the interlevel dielectric. This coating is sufficiently thin so as to obviate the need for additional planarization by polishing, while providing protection against oxidation and surface, or interface, diffusion of Cu which has been identified by the inventors as the leading contributor to metal line failure by electromigration and thermal stress voiding. Also, the metal layer increases the adhesion strength between the Cu and dielectric so as to further increase lifetime and facilitate process yield. The free surface is a direct result of the CMP (chemical mechanical polishing) in a damascene process or in a dry etching process by which Cu wiring is patterned. It is proposed that the metal capping layer be deposited by a selective process onto the Cu to minimize further processing.

Abstract: A ball-limiting metallurgy includes a substrate, a barrier layer formed over the substrate, an adhesion layer formed over the barrier layer, a first solderable layer formed over the adhesion layer, a diffusion barrier layer formed over the adhesion layer, and a second solderable layer formed over the diffusion barrier layer.

Abstract: An electrical structure including a substrate and an interconnect. The substrate includes an electrically conductive and corrosion resistant metallic layer on a metal layer. The interconnect is electrically coupled to the metallic layer. A top surface of the metallic layer is above a top surface of the substrate and a bottom surface of the metallic layer is in direct mechanical contact with a first portion of a top surface of the metal layer. The metal layer is unalloyed and includes a metal.

Abstract: A method to selectively metallize polyimide with an all-electroless process.

Abstract: A self-aligned (i.e., spatially selective) process for fabricating a corrosion-resistant conductive pad on a substrate, and an associated structure that includes an interconnect to allow a terminal connection to the conductive pad (e.g., a chip-to-package connection). The conductive pad may include a metal such as copper, aluminum, or tungsten. Examples of a relevant interconnect include a wirebond interconnect and a controlled collapse chip connection (C4) interconnect. The self-aligned process generates a metallic layer on an initially exposed metal layer, wherein the metallic layer is electrically conductive and corrosion resistant. The metallic layer includes an alloy or an unalloyed metal. The metal layer may include copper.

Abstract: A self-aligned process for fabricating a corrosion-resistant conductive pad on a substrate, and a structure that includes an interconnect to allow a terminal connection to the pad. The process generates a metallic layer on an initially exposed metal layer. The metallic layer is electrically conductive and corrosion resistant. The process includes providing a substrate having a metal layer with an exposed surface, depositing a second metal layer on the exposed surface, annealing the substrate to alloy a portion of the metal layer that includes the exposed surface and a portion of the second metal layer, and removing the unalloyed portion of the second metal layer. An alternative process includes providing a metal layer on the substrate, and electroless plating a corrosion-resistant metal or alloy on the metal layer. The alternative process may additionally include electroless plating a second corrosion-resistant metal on the corrosion-resistant metal or alloy.

Abstract: A method for testing integrated circuit chips with probe wires on flat solder bumps and IC chips that are equipped with flat solder bumps are disclosed. In the method, an IC chip that has a multiplicity of bond pads and a multiplicity of flat solder bumps are first provided in which each of the solder bumps has a height less than ½ of its diameter on the multiplicity of bond pads. The probe wires can thus be easily used to contact the increased target area on the solder bumps for establishing electrical connection with a test circuit. The probe can further be conducted easily with all the Z height of the bumps are substantially equal. The height of the solder bumps may be suitably controlled by either a planarization process in which soft solder bumps are compressed by a planar surface, or solder bumps are formed in an in-situ mold by either a MSS or an electroplating process for forming solder bumps in the shape of short cylinders.

Abstract: A method for testing integrated circuit chips with probe wires on flat solder bumps and IC chips that are equipped with flat solder bumps are disclosed. In the method, an IC chip that has a multiplicity of bond pads and a multiplicity of flat solder bumps are first provided in which each of the solder bumps has a height less than ½ of its diameter on the multiplicity of bond pads. The probe wires can thus be easily used to contact the increased target area on the solder bumps for establishing electrical connection with a test circuit. The probe can further be conducted easily with all the Z height of the bumps are substantially equal. The height of the solder bumps may be suitably controlled by either a planarization process in which soft solder bumps are compressed by a planar surface, or solder bumps are formed in an in-situ mold by either a MSS or an electroplating process for forming solder bumps in the shape of short cylinders.

Abstract: An advanced back-end-of-line (BEOL) integration scheme for semiconductor devices using very low-k dielectric materials is disclosed. The disclosed method for forming a metal interconnect structure in a semiconductor integrated circuit device comprises forming the metal interconnects using a through-mask plating (TMP) process, and encapsulating the interconnects with a barrier layer by selectively depositing a barrier layer material using an electroless liner plating process or by non-selectively depositing a blanket insulator diffusion barrier layer using PVD or CVD techniques.

Abstract: A method for direct chip attach of a semiconductor chip to a circuit board by using solder bumps and an underfill layer is disclosed. In the method, a layer of in-situ polymeric mold material is first screen printed on the top surface of the semiconductor chip exposing a multiplicity of bond pads. The in-situ polymeric mold layer is formed with a multiplicity of apertures which are then filled with solder material in a molten solder screening process to form solder bumps. A thin flux-containing underfill material layer is then placed on top of a circuit board over a plurality of conductive pads which are arranged in a mirror image to the bond pads on the semiconductor chip. The semiconductor chip and the circuit board are then pressed together with the underfill layer inbetween and heated to a reflow temperature of higher than the melting temperature of the solder material until electrical communication is established between the bond pads and the conductive pads.

Abstract: A self-aligned (i.e., spatially selective) process for fabricating a corrosion-resistant conductive pad on a substrate, and an associated structure that includes an interconnect to allow a terminal connection to the conductive pad (e.g., a chip-to-package connection). The conductive pad may include a metal such as copper, aluminum, or tungsten. Examples of a relevant interconnect include a wirebond interconnect and a controlled collapse chip connection (C4) interconnect. The self-aligned process generates a metallic layer on an initially exposed metal layer, wherein the metallic layer is electrically conductive and corrosion resistant. The metallic layer includes an alloy or an unalloyed metal. The metal layer may include copper.

Abstract: The invention provides a process to increase the reliability of BEOL interconnects. The process comprises forming an array of conductors on a dielectric layer on a wafer substrate, polishing the upper surface so that the surfaces of the conductors are substantially co-planar with the upper surface of the dielectric layer, forming an alloy film on the upper surfaces of the conductors, and brush cleaning the upper surfaces of the conductors and the dielectric layer.

Abstract: A self-aligned (i.e., spatially selective) process for fabricating a corrosion-resistant conductive pad on a substrate, and an associated structure that includes an interconnect to allow a terminal connection to the conductive pad (e.g., a chip-to-package connection). The conductive pad may include a metal such as copper, aluminum, or tungsten. The self-aligned process generates a metallic layer on an initially exposed metal layer, wherein the metallic layer is electrically conductive and corrosion resistant. The process may be accomplished by providing a substrate having a metal layer with an exposed surface, depositing a second metal layer on the exposed surface, annealing the substrate to alloy a portion of the metal layer that includes the exposed surface and a portion of the second metal layer, and removing the unalloyed portion of the second metal layer.

Abstract: Circuit boards are manufactured by forming a substrate with a dielectric surface and laminating a metal foil onto the substrate. The metal foil is patterned to form a first wiring layer. A permanent photoimagable dielectric layer is formed over the wiring layer and via holes are formed through the dielectric layer over pads and conductors of the wiring layer. Holes are formed through the substrate and substrate surfaces including the photoimagable dielectric, walls of the via holes, and walls of the through holes subjected to an electroless copper plating process. The process includes seeding the surface, coating the surface with a first solution containing surfactant and electroplating in a second solution in which the level of surfactant is regulated by determining the surface tension and metering surfactant addition to the second solution depending on the determination of surface tension.

Abstract: A semiconductor structure, having a semiconductor dielectric material having an opening. A first material lining the opening, the first material comprising MXY, where M is selected from the group consisting of cobalt and nickel, X is selected from the group consisting of tungsten and silicon and Y is selected from the group consisting of phosphorus and boron and a second material filling the lined dielectric material.

Abstract: A method for direct chip attach of a semiconductor chip to a circuit board by using solder bumps and an underfill layer is disclosed. In the method, a layer of in-situ polymeric mold material is first screen printed on the top surface of the semiconductor chip exposing a multiplicity of bond pads. The in-situ polymeric mold layer is formed with a multiplicity of apertures which are then filled with solder material in a molten solder screening process to form solder bumps. A thin flux-containing underfill material layer is then placed on top of a circuit board over a plurality of conductive pads which are arranged in a mirror image to the bond pads on the semiconductor chip. The semiconductor chip and the circuit board are then pressed together with the underfill layer inbetween and heated to a reflow temperature of higher than the melting temperature of the solder material until electrical communication is established between the bond pads and the conductive pads.

Abstract: A damascene interconnect containing a dual etch stop/diffusion barrier. The conductive material of the damascene interconnect is capped with a conductive metal diffusion barrier cap, typically using electroless deposition, and, optionally, with a dielectric etch-stop layer. An optional chemical mechanical polish-stop layer may also be present. The different methods of the invention allow the CMP stop, reactive-ion etch stop, and metal diffusion barrier requirements of the different layers to be decoupled. A preferred conductive material is copper.

Abstract: A method for direct chip attach of a semiconductor chip to a circuit board by using solder bumps and an underfill layer is disclosed. In the method, a layer of in-situ polymeric mold material is first screen printed on the top surface of the semiconductor chip exposing a multiplicity of bond pads. The in-situ polymeric mold layer is formed with a multiplicity of apertures which are then filled with solder material in a molten solder screening process to form solder bumps. A thin flux-containing underfill material layer is then placed on top of a circuit board over a plurality of conductive pads which are arranged in a mirror image to the bond pads on the semiconductor chip. The semiconductor chip and the circuit board are then pressed together with the underfill layer inbetween and heated to a reflow temperature of higher than the melting temperature of the solder material until electrical communication is established between the bond pads and the conductive pads.

Abstract: A method of manufacturing integrated circuits wherein a conductive structure in a topmost semiconductive layer of an integrated circuit is provided having a thickness greater than or equal to 1.5 &mgr;m. The thickness of the conductive structure is sufficiently great as to effectively protect any layers beneath the topmost semiconductive layer from damage from pressure, such as pressure applied by testing probes. In a preferred embodiment, traditional aluminum TD leveling is discarded in favor of gold deposited upon the thickened conductive layer.

Abstract: A method for preparing a copper pad surface for electrical connection that has superior diffusion barrier and adhesion properties is provided. In the method, a copper pad surface is first provided that has been cleaned by an acid solution, a protection layer of a phosphorus or boron-containing metal alloy is then deposited on the copper pad surface, and then an adhesion layer of a noble metal is deposited on top of the protection layer. The protection layer may be a single layer, or two or more layers intimately joined together formed of a phosphorus or boron-containing metal alloy such as Ni-P, Co-P, Co-W-P, Co-Sn-P, Ni-W-P, Co-B, Ni-B, Co-Sn-B, Co-W-B and Ni-W-B to a thickness between about 1,000 Å and about 10,000 Å. The adhesion layer can be formed of a noble metal such as Au, Pt, Pd and Ag to a thickness between about 500 Å and about 4,000 Å.