Abstract: An integrated circuit device includes a main integrated circuit die having functional circuitry configured to communicate over a network through one or more high-speed communications interfaces, and at least one secondary integrated circuit die including serial interface circuitry. Each integrated circuit die among the at least one secondary integrated circuit die is mounted on a first surface of the main integrated circuit die, and first metallization connections extend along one or more first through-silicon vias between the functional circuitry and the serial interface circuitry of the at least one secondary integrated circuit die. The first metallization connections may be configured to provide data from the main die to the secondary die, and the secondary die may be configured to communicate data between the integrated circuit device and a remote integrated circuit device. Second metallization connections extend between the serial interface circuitry of and terminals of the main integrated circuit die.

Abstract: Apparatus and methods for clock domain crossing between a first clock domain and a second clock domain. The apparatus comprises a first control logic element for processing a handshake signal and producing a first arbiter input signal. Concurrently a second control logic element processes a second handshake signal and produces a second arbiter input signal. Exemplary embodiments include exactly one arbiter element inputting the first arbiter input signal, inputting the second arbiter input signal, outputting a first clocking signal to the first sequential element and outputting a second clocking signal to the second sequential element. For managing metastability by controlling the timing of the clocking inputs of the sequential devices, the apparatus includes a first controllable lock delay element selected to satisfy the setup constraint of the second sequential element, and a second controllable lock delay element selected to satisfy the hold constraint of the second sequential element.

Abstract: Apparatus and methods for clock domain crossing between a first clock domain and a second clock domain. The apparatus comprises a first control logic element for processing a handshake signal and producing a first arbiter input signal. Concurrently a second control logic element processes a second handshake signal and produces a second arbiter input signal. Exemplary embodiments include exactly one arbiter element inputting the first arbiter input signal, inputting the second arbiter input signal, outputting a first clocking signal to the first sequential element and outputting a second clocking signal to the second sequential element. For managing metastability by controlling the timing of the clocking inputs of the sequential devices, the apparatus includes a first controllable lock delay element selected to satisfy the setup constraint of the second sequential element, and a second controllable lock delay element selected to satisfy the hold constraint of the second sequential element.