Abstract: A method and apparatus for aligning surface mounted optoelectric devices on a printed circuit board are disclosed. An optical transmitter and an optical receiver are added to the surface mounted optoelectric device. Also, a fiber optic cable is embedded within a printed circuit board. The length of the fiber optic cable is at least equivalent to a distance between the optical transmitter and the optical receiver placed on the surface mounted optoelectric device. An orientation of the surface mounted optoelectric device is aligned on the printed circuit board such that an optical signal transmitting from the optical transmitter can be received by the optical receiver via the fiber optic cable.

Abstract: A driver circuit includes both a conventional three state mode of operation and a five state operating mode. In the three state mode of operation, the output of the driver can be in logical 0 or logical 1 "voltage source" states, as well as a very high impedance state. In addition to these three states, the output of the driver in the five state mode of operation can also be in logical 1 and logical 0 "current source" states. The voltage source states are characterized by low output impedance (e.g., 30 Ohms), while the current source states are characterized by higher output impedance (e.g., 600 Ohms). The driver circuit is particularly useful for eliminating turnaround cycles on a multiplexed address/data bus. When coupled to such a bus, the clock line is used to select the voltage source mode during the first half of the clock cycle, and the current source mode during the last half of the clock cycle.

Abstract: An extended PCI bus (100) accepts both standard 33 MHz (101-102) and extended 66 MHz (103-104) PCI I/O devices, and permits the intermixing and interoperability of both types of devices on the same bus. Each extended 66 MHz initiator device (103) includes a target memory (205) that is programmed at boot up to include a list of address ranges of all extended 66 MHz devices. Each extended 66 MHz device includes a clock multiplier (202) that generates an internal 66 MHz clock signal by doubling the 33 MHz bus clock frequency. This clock multiplier may be in the form of a simple edge detecting frequency doubler (FIG. 4), or a phase locked loop (FIG. 5) that can also provide for phase adjustments to alter the skew between the bus and internal clocks. To transfer data between two extended 66 MHz devices, an extended initiator device sends, during the address/control phase of the bus cycle, a fast read or write command to the extended target device over the C/BE lines of the bus.

Abstract: A Level Sensitive Scan Design (LSSD) Shift Register Latch pair implemented in current switch logic is disclosed. The arrangement is characterized by the logic used to control the L1 and L2 latches being implemented in Differential Cascode Current Switch logic and the L1/L2 latches being coupled to only one current source. A "merged" L1/L2 latch arrangement employing only one current source is provided for an LSSD testing environment.