Patents by Inventor Carlos Obregon

Carlos Obregon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240135402
    Abstract: A method can include establishing, by a computing system, a secure electronic network connection to an electronic agent running configured to access the dataset to dynamically generate the metadata related to the dataset on a client computing system. A method can include receiving, by the computing system, from the electronic agent via the secure electronic network connection, metadata related to a dataset, the metadata comprising a plurality of attributes of the dataset and a summary of the dataset. A method can include applying a valuation model to the metadata to determine an estimated value of the dataset, the valuation model comprising a machine learning model trained using marketplace data comprising sales prices and attributes of one or more datasets, wherein the model is trained to output the sales prices of the one or more datasets. A method can include determining, an estimated value of the dataset.
    Type: Application
    Filed: October 19, 2023
    Publication date: April 25, 2024
    Inventors: Lauren S. Cascio, Charles E. Fisher, Christopher M. Ensey, Michael S. Sobeck, Michael S. Blake, Gbolahan Promise Dada, Luis A. Obregon Mogollon, Rogfel Thompson Martínez, Antonio Martin Martinez, Carlos Valenzuela Lembach
  • Patent number: 5546021
    Abstract: A 3 state BiCMOS output buffer (100) with power down capability has been provided. The buffer includes an input stage (102), responsive to an input signal, an output coupled to both a pull-up driver (114), and an output pull-down driver (116) wherein the drivers provide an output signal at an output of the buffer in response to the input signal. Additionally, the buffer includes a power down sense circuit (108), coupled to a power supply node (118), for turning off an output pull-up transistor (214) when the power supply node is powered down and thus eliminating leakage paths within the buffer. The buffer also includes a noise limiting circuit (112) for slowing down a high to low transition at the output of the buffer thereby reducing the switching noise of the buffer while not affecting the overall speed of the buffer.
    Type: Grant
    Filed: February 14, 1994
    Date of Patent: August 13, 1996
    Assignee: Motorola, Inc.
    Inventors: Daniel T. Bizuneh, Carlos Obregon, Michael A. Wells, Eric D. Neely