Abstract: An oversize ferroelectric capacitor is located against the contact hole to the MOSFET source/drain in a DRAM. A barrier layer made of titanium nitride, titanium tungsten, tantalum, titanium, tungsten, molybdenum, chromium, indium tin oxide, tin dioxide, ruthenium oxide, silicon, silicide, or polycide lies between the ferroelectric layer and the source drain. The barrier layer may act as the bottom electrode of the ferroelectric capacitor, or a separate bottom electrode made of platinum may be used. In another embodiment in which the barrier layer forms the bottom electrode, an oxide layer less than 5 nm thick is located between the barrier layer and the ferroelectric layer and the barrier layer is made of silicon, silicide, or polycide. A thin silicide layer forms and ohmic contact between the barrier layer and the source/drain. The capacitor and the barrier layer are patterned in a single mask step. The ends of the capacitor are stepped or tapered.

Abstract: An oversize ferroelectric capacitor is located against the contact hole to the MOSFET source/drain in a DRAM. A barrier layer made of titanium nitride, titanium tungsten, tantalum, titanium, tungsten, molybdenum, chromium, indium tin oxide, tin dioxide, ruthenium oxide, silicon, silicide, or polycide lies between the ferroelectric layer and the source drain. The barrier layer may act as the bottom electrode of the ferroelectric capacitor, or a separate bottom electrode made of platinum may be used. In another embodiment in which the barrier layer forms the bottom electrode, an oxide layer less than 5 nm thick is located between the barrier layer and the ferroelectric layer and the barrier layer is made of silicon, silicide, or polycide. A thin silicide layer forms and ohmic contact between the barrier layer and the source/drain. The capacitor and the barrier layer are patterned in a single mask step. The ends of the capacitor are stepped or tapered.

Abstract: An electrically programmable antifuse element using ferroelectric materials for the insulative dielectric layer, methods for producing same, and an integrated circuit applying a plurality of ferroelectric antifuse elements in a two dimensional matrix of rows and columns for use as a programmable logic device (PLD) or as a programmable read-only memory (PROM). A ferroelectric material is formed between two conductive electrodes to create a ferroelectric antifuse element. In an alternative embodiment, a plurality of chemically distinct materials is layered to form the dielectric layer. The combined application of an AC electric field and a DC electric field breaks down the ferroelectric material to form a low-resistance conductive filament. The synergy of the two electric fields permits programming antifuse elements of the present invention by applying DC electric fields as low as 2 volts amplitude.

Abstract: A wristwatch contains communication and memory circuitry and a transmitter. The memory circuit stores a personal identification number of a single user. The communication and memory circuitry is driven by the same battery which powers the timekeeping structure of the watch. A transmitter transmits data from the reader to the wristwatch, placed proximate thereto. The reader has a keypad by which the user can enter a personal identification number, and the watch compares the transmitted number to the user-entered number. If the numbers match, a transaction may occur.