Abstract: An integrated circuit (IC) die comprises a sensor, which includes a pulse generator and a pulse expander. The pulse generator comprises gate circuits coupled to each other in an in-series arrangement. An input of the pulse generator is coupled to receive a voltage and the pulse generator is to generate a first signal based on the voltage. The pulse generator is to generate a first pulse of the first signal based on an event wherein radiation from a laser is incident upon the pulse generator. The pulse expander is coupled to receive the first signal from the pulse generator and to generate a second signal based on the first signal, wherein a second pulse of the second signal is based on the first pulse. A first duration of the first pulse is less than a second duration of the second pulse.

Abstract: A voltage detection circuit includes a tunable delay circuit that receives a supply voltage and that generates a delayed signal in response to an input signal. A control circuit causes a first adjustment in a delay provided by the tunable delay circuit to the delayed signal. An error detection circuit generates an error indication in an error signal in response to a change in a timing of the delayed signal relative to a clock signal caused by the first adjustment in the delay provided to the delayed signal. The control circuit causes a second adjustment in the delay provided by the tunable delay circuit to the delayed signal in response to the error indication. The error detection circuit causes the error signal to be indicative of the supply voltage reaching a threshold voltage after the second adjustment in the delay.

Abstract: An apparatus, system, and method for are provided. A device includes a first tunable replica circuit configured to detect an undervoltage and overclocking event, a second tunable replica circuit configured to detect an overvoltage and underclocking event, and a countermeasures component configured to alter a circuit of the device responsive to detection of the undervoltage and overclocking event or the overvoltage and underclocking event.

Abstract: A near memory compute system includes multiple computation nodes, such as nodes for parallel distributed processing. The nodes include a memory device to store data and compute hardware to perform a computation on the data. Error correction code (ECC) logic performs ECC on the data prior to computation on the data by the compute hardware. The node also includes residue check logic to perform a residue check on a result of the computation.

Abstract: A detection circuit includes a tunable delay circuit that generates a delayed signal and that receives a supply voltage. The detection circuit includes a control circuit that adjusts a delay provided by the tunable delay circuit to the delayed signal. The detection circuit includes a time-to-digital converter circuit that converts the delay provided by the tunable delay circuit to the delayed signal to a digital code and adjusts the digital code based on changes in the supply voltage. The control circuit causes the tunable delay circuit to maintain the delay provided to the delayed signal constant in response to the digital code reaching an alignment value. The detection circuit may continuously monitor timing margin of a data signal relative to a clock signal and update the digital code in every clock cycle. The detection circuit may be a security sensor that detects changes in the supply voltage.

Abstract: Embodiments are directed to countermeasures against hardware side-channel attacks on cryptographic operations. An embodiment of an apparatus includes multiple crypto cores; and a current source including multiple current source blocks, the current source blocks including a respective current source block associated with each of the crypto cores, and wherein the current sources blocks are switchable to switch on a current source block associated with each active core of the multiple crypto cores and to switch off a current source associated with each inactive core of the multiple cryptographic cores.

Abstract: A voltage detection circuit includes a tunable delay circuit that receives a supply voltage and that generates a delayed signal in response to an input signal. A control circuit causes a first adjustment in a delay provided by the tunable delay circuit to the delayed signal. An error detection circuit generates an error indication in an error signal in response to a change in a timing of the delayed signal relative to a clock signal caused by the first adjustment in the delay provided to the delayed signal. The control circuit causes a second adjustment in the delay provided by the tunable delay circuit to the delayed signal in response to the error indication. The error detection circuit causes the error signal to be indicative of the supply voltage reaching a threshold voltage after the second adjustment in the delay.

Abstract: Switched adaptive clocking is provided. A switched adaptive clocking circuit includes a digitally controlled oscillator, a clock generator and a glitch-free multiplexer. The switched adaptive clocking circuit to adaptively switch a source of an output clock from a main clock generated by a clock source to a digitally controlled oscillator clock generated by a digitally controlled oscillator upon detection of a voltage droop, and to quickly switch back to the main clock after recovery from the voltage droop.

Abstract: Embodiments are directed to countermeasures against hardware side-channel attacks on cryptographic operations. An embodiment of an apparatus includes multiple crypto cores; and a current source including multiple current source blocks, the current source blocks including a respective current source block associated with each of the crypto cores, and wherein the current sources blocks are switchable to switch on a current source block associated with each active core of the multiple crypto cores and to switch off a current source associated with each inactive core of the multiple cryptographic cores.

Abstract: Embodiments include circuits, apparatuses, and systems for voltage level shifter monitors. In embodiments, a voltage level shifter monitor may include a first signal generator to generate a signal in a first voltage domain, a second signal generator to generate a second signal in a second voltage domain, where the second digital signal corresponds to the first digital signal, a voltage level shifter replica circuit to convert the first digital signal from the first voltage domain to a third digital signal in the second voltage domain, and a comparison circuit to generate a digital error signal based at least in part on the second digital signal and the third digital signal. Other embodiments may be described and claimed.

Abstract: An apparatus is described. The apparatus includes a semiconductor chip. The semiconductor chip includes a memory having multiple storage cells. The storage cells are to receive a supply voltage. The semiconductor chip includes supply voltage retention circuitry. The supply voltage retention circuitry is to determine a level of the supply voltage at which the storage cells are able to retain their respective data. The supply voltage retention circuitry is to receive the supply voltage during a stress mode of the supply voltage retention circuitry. The supply voltage retention circuitry is to more weakly retain its stored information than the storage cells during a measurement mode at which the level is determined.

Abstract: An apparatus is provided which includes: a first power supply node; a second power supply node; a memory bit-cell coupled to the second power supply node; a circuitry coupled to the first and second power supply nodes, the circuitry to operate in a diode-connected mode; and a transistor coupled in parallel to the circuitry, wherein the transistor is controllable by a digital signal such that when the transistor is to turn on, it is to apply voltage and/or current stress to the memory bit-cell.

Abstract: An apparatus is provided which includes: a first power supply node; a second power supply node; a memory bit-cell coupled to the second power supply node; a circuitry coupled to the first and second power supply nodes, the circuitry to operate in a diode-connected mode; and a transistor coupled in parallel to the circuitry, wherein the transistor is controllable by a digital signal such that when the transistor is to turn on, it is to apply voltage and/or current stress to the memory bit-cell.

Abstract: Embodiments include circuits, apparatuses, and systems for voltage level shifter monitors. In embodiments, a voltage level shifter monitor may include a first signal generator to generate a signal in a first voltage domain, a second signal generator to generate a second signal in a second voltage domain, where the second digital signal corresponds to the first digital signal, a voltage level shifter replica circuit to convert the first digital signal from the first voltage domain to a third digital signal in the second voltage domain, and a comparison circuit to generate a digital error signal based at least in part on the second digital signal and the third digital signal. Other embodiments may be described and claimed.

Abstract: An apparatus is described. The apparatus includes a semiconductor chip. The semiconductor chip includes a memory having multiple storage cells. The storage cells are to receive a supply voltage. The semiconductor chip includes supply voltage retention circuitry. The supply voltage retention circuitry is to determine a level of the supply voltage at which the storage cells are able to retain their respective data. The supply voltage retention circuitry is to receive the supply voltage during a stress mode of the supply voltage retention circuitry. The supply voltage retention circuitry is to more weakly retain its stored information than the storage cells during a measurement mode at which the level is determined.

Abstract: Described is a physically unclonable functional circuit comprising: a resistive memory device (e.g., an MTJ device) having at least two terminals; a transistor coupled to one of the at least two terminals of the resistive memory device; and an analog-to-digital converter (ADC) having an input coupled to the one of the at least two terminals of the resistive memory device.

Abstract: Described is an apparatus including memory cell with retention using resistive memory. The apparatus comprises: memory element including a first inverting device cross-coupled to a second inverting device; a restore circuit having at least one resistive memory element, the restore circuit coupled to an output of the first inverting device; a third inverting device coupled to the output of the first inverting device; a fourth inverting device coupled to an output of the third inverting device; and a save circuit having at least one resistive memory element, the save circuit coupled to an output of the third inverting device.

Abstract: Some embodiments include apparatus and methods using a first ring oscillator, a second ring oscillator, and circuit coupled to the first and second ring oscillators. The first ring oscillator includes a first memory cell and a first plurality of stages coupled to the first memory cell. The second ring oscillator includes a second memory cell and a second plurality of stages coupled to the second memory cell. The circuit includes a first input node coupled to an output node of the first ring oscillator and a second input node coupled to an output node of the second ring oscillator. In one of such embodiments, the circuit can operate to generate identification information to authenticate the apparatus.

Abstract: Described is a physically unclonable functional circuit comprising: a resistive memory device (e.g., an MTJ device) having at least two terminals; a transistor coupled to one of the at least two terminals of the resistive memory device; and an analog-to-digital converter (ADC) having an input coupled to the one of the at least two terminals of the resistive memory device.

Abstract: Embodiments include apparatuses, methods, and systems for voltage level shifting a data signal between a low voltage domain and a high voltage domain. In embodiments, a voltage level shifter circuit may include adaptive keeper circuitry, enhanced interruptible supply circuitry, and/or capacitive boosting circuitry to reduce a minimum voltage of the low voltage domain that is supported by the voltage level shifter circuit. Other embodiments may be described and claimed.