Abstract: Technologies for a field effect transistor (FET) with a ferroelectric gate dielectric are disclosed. In an illustrative embodiment, a perovskite stack is grown on a buffer layer as part of manufacturing a transistor. The perovskite stack includes one or more doped semiconductor layers alternating with other lattice-matched layers, such as undoped semiconductor layers. Growing the doped semiconductor layers on lattice-matched layers can improve the quality of the doped semiconductor layers. The lattice-matched layers can be preferentially etched away, leaving the doped semiconductor layers as fins for a ribbon FET. In another embodiment, an interlayer can be deposited on top of a semiconductor layer, and a ferroelectric layer can be deposited on the interlayer. The interlayer can bridge a gap in lattice parameters between the semiconductor layer and the ferroelectric layer.

Abstract: Technologies for a transistor with a thin-film ferroelectric gate dielectric are disclosed. In the illustrative embodiment, a transistor has a thin layer of scandium aluminum nitride (ScxAl1-xN) ferroelectric gate dielectric. The channel of the transistor may be, e.g., gallium nitride or molybdenum disulfide. In one embodiment, the ferroelectric polarization changes when voltage is applied and removed from a gate electrode, facilitating switching of the transistor at a lower applied voltage. In another embodiment, the ferroelectric polarization of a gate dielectric of a transistor changes when the voltage is past a positive threshold value or a negative threshold value. Such a transistor can be used as a one-transistor memory cell.

Abstract: In one embodiment, transistor device includes a first source or drain material on a substrate, a semiconductor material on the first source or drain material, a second source or drain material on the semiconductor material, a dielectric layer on the substrate and adjacent the first source or drain material, a ferroelectric (FE) material on the dielectric layer and adjacent the semiconductor material, and a gate material on or adjacent to the FE material. The FE material may be a perovskite material and may have a lattice parameter that is less than a lattice parameter of the semiconductor material.

Abstract: In one embodiment, a transistor device includes a gate material layer on a substrate, a ferroelectric (FE) material layer on the gate material, a semiconductor channel material layer on the FE material layer, a first source/drain material on the FE material layer and adjacent the semiconductor channel material layer, and a second source/drain material on the FE material layer and adjacent the semiconductor channel material layer and on an opposite side of the semiconductor channel material layer from the first source/drain material. A first portion of the FE material layer is directly between the gate material and the first source/drain material, and a second portion of the FE material layer is directly between the gate material and the second source/drain material.

Abstract: A temperature-regulating mattress system provides dynamic adjustment of temperature and other parameters throughout a user's sleep cycle to maximize the quality of the user's sleep, Features of the system may include: (a) heating and cooling temperature regulation (with dynamic custom profiles that control humidity and are dual-zone); (b) smart controls (with remotes and apps that learn from users to optimize settings and work with smart home products such as Alexa and interactive lighting systems); (c) comfort (with a mattress that provide the necessary support for its users); and (d) sensors used for temperature and humidity estimation algorithms, control mechanism, and additional inferences from those sensors (pose, enrichment of biometric sensing data, etc.).

Abstract: A temperature-regulating mattress system provides dynamic adjustment of temperature and other parameters throughout a user's sleep cycle to maximize the quality of the user's sleep, Features of the system may include: (a) heating and cooling temperature regulation (with dynamic custom profiles that control humidity and are dual-zone); (b) smart controls (with remotes and apps that learn from users to optimize settings and work with smart home products such as Alexa and interactive lighting systems); (c) comfort (with a mattress that provide the necessary support for its users); and (d) sensors used for temperature and humidity estimation algorithms, control mechanism, and additional inferences from those sensors (pose, enrichment of biometric sensing data, etc.).