Patents by Inventor Carmelo Condemi
Carmelo Condemi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11868488Abstract: An apparatus, such as a memory system (e.g., a NAND memory system), can have a controller with a first error correction code component and a memory device (e.g., a NAND memory device) coupled to the controller. The memory device can have an array of memory cells, a second error correction code component coupled to the array and configured to correct data from the array, and a cryptographic component coupled to receive the corrected data from the second error correction code component.Type: GrantFiled: November 28, 2022Date of Patent: January 9, 2024Assignee: Micron Technology, Inc.Inventors: Antonino Mondello, Carmelo Condemi, Francesco Tomaiuolo, Tommaso Zerilli
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Patent number: 11722323Abstract: Various examples described herein are directed to systems and methods for generating data values using a NAND flash array. A memory controller may read a number of memory cells at the NAND flash array using an initial read level to generate a first raw string. The memory controller may determine that a difference between a number of bits from the first raw string having a value of logical zero and a number of bits from the first raw string having a value of logical one is greater than a threshold value and read the number of memory cells using a second read level to generate a second raw string. The memory controller may determine that a difference between a number of bits from the second raw string having a value of logical zero and a number of bits from the second raw string having a value of logical one is not greater than a threshold value and applying a cryptographic function using the second raw string to generate a first PUF value.Type: GrantFiled: August 25, 2022Date of Patent: August 8, 2023Assignee: Micron Technology, Inc.Inventors: Antonino Mondello, Tommaso Zerilli, Carmelo Condemi, Francesco Tomaiuolo
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Patent number: 11657877Abstract: An apparatus, such as a memory (e.g., a NAND memory), can have a controller, a volatile counter coupled to the controller, and a non-volatile memory array coupled to the controller. The controller can be configured to write information, other than a count of the counter, in the array each time the count of the counter has been incremented by a particular number of increments. Counts can be monotonic, non-volatile, and power-loss tolerant.Type: GrantFiled: July 2, 2021Date of Patent: May 23, 2023Assignee: Micron Technology, Inc.Inventors: Antonino Mondello, Francesco Tomaiuolo, Carmelo Condemi, Tommaso Zerilli
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Publication number: 20230086754Abstract: An apparatus, such as a memory system (e.g., a NAND memory system), can have a controller with a first error correction code component and a memory device (e.g., a NAND memory device) coupled to the controller. The memory device can have an array of memory cells, a second error correction code component coupled to the array and configured to correct data from the array, and a cryptographic component coupled to receive the corrected data from the second error correction code component.Type: ApplicationFiled: November 28, 2022Publication date: March 23, 2023Inventors: Antonino Mondello, Carmelo Condemi, Francesco Tomaiuolo, Tommaso Zerilli
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Publication number: 20230039804Abstract: Various examples described herein are directed to systems and methods for generating data values using a NAND flash array. A memory controller may read a number of memory cells at the NAND flash array using an initial read level to generate a first raw string. The memory controller may determine that a difference between a number of bits from the first raw string having a value of logical zero and a number of bits from the first raw string having a value of logical one is greater than a threshold value and read the number of memory cells using a second read level to generate a second raw string. The memory controller may determine that a difference between a number of bits from the second raw string having a value of logical zero and a number of bits from the second raw string having a value of logical one is not greater than a threshold value and applying a cryptographic function using the second raw string to generate a first PUF value.Type: ApplicationFiled: August 25, 2022Publication date: February 9, 2023Inventors: Antonino Mondello, Tommasso Zerilli, Carmelo Condemi, Francesco Tomaiuolo
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Patent number: 11514174Abstract: An apparatus, such as a memory system (e.g., a NAND memory system), can have a controller with a first error correction code component and a memory device (e.g., a NAND memory device) coupled to the controller. The memory device can have an array of memory cells, a second error correction code component coupled to the array and configured to correct data from the array, and a cryptographic component coupled to receive the corrected data from the second error correction code component.Type: GrantFiled: January 23, 2019Date of Patent: November 29, 2022Assignee: Micron Technology, Inc.Inventors: Antonino Mondello, Carmelo Condemi, Francesco Tomaiuolo, Tommaso Zerilli
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Patent number: 11469909Abstract: Various examples described herein are directed to systems and methods for generating data values using a NAND flash array. A memory controller may read a number of memory cells at the NAND flash array using an initial read level to generate a first raw string. The memory controller may determine that a difference between a number of bits from the first raw string having a value of logical zero and a number of bits from the first raw string having a value of logical one is greater than a threshold value and read the number of memory cells using a second read level to generate a second raw string. The memory controller may determine that a difference between a number of bits from the second raw string having a value of logical zero and a number of bits from the second raw string having a value of logical one is not greater than a threshold value and applying a cryptographic function using the second raw string to generate a first PUF value.Type: GrantFiled: December 28, 2018Date of Patent: October 11, 2022Assignee: Micron Technology, Inc.Inventors: Antonino Mondello, Tommaso Zerilli, Carmelo Condemi, Francesco Tomaiuolo
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Publication number: 20210335425Abstract: An apparatus, such as a memory (e.g., a NAND memory), can have a controller, a volatile counter coupled to the controller, and a non-volatile memory array coupled to the controller. The controller can be configured to write information, other than a count of the counter, in the array each time the count of the counter has been incremented by a particular number of increments. Counts can be monotonic, non-volatile, and power-loss tolerant.Type: ApplicationFiled: July 2, 2021Publication date: October 28, 2021Inventors: Antonino Mondello, Francesco Tomaiuolo, Carmelo Condemi, Tommaso Zerilli
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Patent number: 11056192Abstract: An apparatus, such as a memory (e.g., a NAND memory), can have a controller, a volatile counter coupled to the controller, and a non-volatile memory array coupled to the controller. The controller can be configured to write information, other than a count of the counter, in the array each time the count of the counter has been incremented by a particular number of increments. Counts can be monotonic, non-volatile, and power-loss tolerant.Type: GrantFiled: December 21, 2018Date of Patent: July 6, 2021Assignee: Micron Technology, Inc.Inventors: Antonino Mondello, Francesco Tomaiuolo, Carmelo Condemi, Tommaso Zerilli
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Publication number: 20200233967Abstract: An apparatus, such as a memory system (e.g., a NAND memory system), can have a controller with a first error correction code component and a memory device (e.g., a NAND memory device) coupled to the controller. The memory device can have an array of memory cells, a second error correction code component coupled to the array and configured to correct data from the array, and a cryptographic component coupled to receive the corrected data from the second error correction code component.Type: ApplicationFiled: January 23, 2019Publication date: July 23, 2020Inventors: Antonino Mondello, Carmelo Condemi, Francesco Tomaiuolo, Tommaso Zerilli
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Publication number: 20200213138Abstract: Various examples described herein are directed to systems and methods for generating data values using a NAND flash array. A memory controller may read a number of memory cells at the NAND flash array using an initial read level to generate a first raw string. The memory controller may determine that a difference between a number of bits from the first raw string having a value of logical zero and a number of bits from the first raw string having a value of logical one is greater than a threshold value and read the number of memory cells using a second read level to generate a second raw string. The memory controller may determine that a difference between a number of bits from the second raw string having a value of logical zero and a number of bits from the second raw string having a value of logical one is not greater than a threshold value and applying a cryptographic function using the second raw string to generate a first PUF value.Type: ApplicationFiled: December 28, 2018Publication date: July 2, 2020Inventors: Antonino Mondello, Tommaso Zerilli, Carmelo Condemi, Francesco Tomaiuolo
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Publication number: 20200202944Abstract: An apparatus, such as a memory (e.g., a NAND memory), can have a controller, a volatile counter coupled to the controller, and a non-volatile memory array coupled to the controller. The controller can be configured to write information, other than a count of the counter, in the array each time the count of the counter has been incremented by a particular number of increments. Counts can be monotonic, non-volatile, and power-loss tolerant.Type: ApplicationFiled: December 21, 2018Publication date: June 25, 2020Inventors: Antonino Mondello, Francesco Tomaiuolo, Carmelo Condemi, Tommaso Zerilli
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Publication number: 20040130953Abstract: The nonvolatile storage device is made up of a memory array divided into a plurality of data-storage units and a plurality of redundancy-storage units for replacing respective failed data-storage units. A control unit detects the functionality of the data-storage units and, in case of failure, enables a redundancy-detection unit having a plurality of volatile-memory elements connected through a sequential daisy-chain connection. A nonvolatile memory unit stores, in a nonvolatile way, the redundancy information through a data bus, connected both to the redundancy-detection unit and to the nonvolatile memory unit; in the event of failure, the redundancy-detection unit transfers the addresses of the failed data-storage unit to the nonvolatile memory unit for their nonvolatile storage.Type: ApplicationFiled: August 11, 2003Publication date: July 8, 2004Applicant: STMicroelectronics S.r.l.Inventors: Luca De Ambroggi, Carmelo Condemi
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Interleaved memory device for sequential access synchronous reading with simplified address counters
Patent number: 6452864Abstract: An interleaved memory includes an array of memory cells divided into a first bank of memory cells and a second bank of memory cells. The interleaved memory operates in a burst access mode. A first address counter is coupled to the first bank of memory cells, and an address register is coupled to the first address counter and to the second bank of memory cells. A timing circuit generates increment pulses to the first address counter so that a first random access asynchronous read cycle starts with the first bank of memory cells. A function of an address counter for the second bank of memory cells is being performed by coping contents of the first address counter to the address register.Type: GrantFiled: January 31, 2001Date of Patent: September 17, 2002Assignee: STMicroelectonics S.R.L.Inventors: Carmelo Condemi, Fabrizio Campanale, Salvatore Nicosia, Francesco Tomaiuolo, Luca Giuseppe De Ambroggi, Promod Kumar -
INTERLEAVED MEMORY DEVICE FOR SEQUENTIAL ACCESS SYNCHRONOUS READING WITH SIMPLIFIED ADDRESS COUNTERS
Publication number: 20020126563Abstract: An interleaved memory includes an array of memory cells divided into a first bank of memory cells and a second bank of memory cells. The interleaved memory operates in a burst access mode. A first address counter is coupled to the first bank of memory cells, and an address register is coupled to the first address counter and to the second bank of memory cells. A timing circuit generates increment pulses to the first address counter so that a first random access asynchronous read cycle starts with the first bank of memory cells. A function of an address counter for the second bank of memory cells is being performed by coping contents of the first address counter to the address register.Type: ApplicationFiled: January 31, 2001Publication date: September 12, 2002Applicant: STMicroelectronics S.r.l.Inventors: Carmelo Condemi, Fabrizio Campanale, Salvatore Nicosia, Francesco Tomaiuolo, Luca Giuseppe De Ambroggi, Promod Kumar -
Patent number: 6366634Abstract: An address binary counter for an interleaved having an array of memory cells being divided into a first bank of memory cells and a second bank of memory cells includes as many stages as the bits that may be stored in the memory cells of a row of one of the banks, and a carry calculation network. The interleaved memory operates in a burst access mode enabled by an enabling signal. The carry calculation network includes an ordered group of independent carry generators. Each independent carry generator includes a certain number of stages, with each stage having inputs receiving its own enabling bit and a number of consecutive bits of a row of the bank equal to the number of stages, orderly starting from the least significant bit. The enabling bit of the first carry generator of the ordered group is the enabling signal, and the enabling bit of any other carry generator of the ordered group is the logic AND of the enabling signal and of the input bits of the preceding carry generator of the ordered group.Type: GrantFiled: January 31, 2001Date of Patent: April 2, 2002Assignee: STMicroelectronics S.R.L.Inventors: Luca Giuseppe De Ambroggi, Salvatore Nicosia, Francesco Tomaiuolo, Fabrizio Campanale, Promod Kumar, Carmelo Condemi
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Patent number: 6324098Abstract: A reading circuit for nonvolatile memory cells, including a current-to-voltage converter, having an array load, connected to a memory cell, and a reference load connected to a reference generator. The array load and the reference load include PMOS transistors presenting an array shape factor (W/L)F and, respectively, a reference shape factor (W/L)R. The reading circuit further includes a charge pump that supplies a biasing voltage to a gate terminal of the memory cell. The biasing voltage is proportional to and higher than a supply voltage VDD. The ratio between the array shape factor (W/L)F and the reference shape factor (W/L)R is a non-integer.Type: GrantFiled: April 11, 2000Date of Patent: November 27, 2001Assignee: STMicroelectronics S.R.L.Inventors: Carmelo Condemi, Michele La Placa, Ignazio Martines
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Publication number: 20010036244Abstract: An address binary counter for an interleaved having an array of memory cells being divided into a first bank of memory cells and a second bank of memory cells includes as many stages as the bits that may be stored in the memory cells of a row of one of the banks, and a carry calculation network. The interleaved memory operates in a burst access mode enabled by an enabling signal. The carry calculation network includes an ordered group of independent carry generators. Each independent carry generator includes a certain number of stages, with each stage having inputs receiving its own enabling bit and a number of consecutive bits of a row of the bank equal to the number of stages, orderly starting from the least significant bit. The enabling bit of the first carry generator of the ordered group is the enabling signal, and the enabling bit of any other carry generator of the ordered group is the logic AND of the enabling signal and of the input bits of the preceding carry generator of the ordered group.Type: ApplicationFiled: January 31, 2001Publication date: November 1, 2001Applicant: STMicroelectronics S.r.l.Inventors: Luca Giuseppe De Ambroggi, Salvatore Nicosia, Francesco Tomaiuolo, Fabrizio Campanale, Promod Kumar, Carmelo Condemi
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Patent number: 6310801Abstract: A method for addressing redundant columns in a nonvolatile memory, which receives, at inputs, selection addresses and comprises a plurality of redundant columns, each including a respective bit line and a plurality of memory cells connected to the bit line. The addressing method comprises the steps of: detecting a transition in the selection addresses; starting charging of all the bit lines upon detection of the transition in the addresses; then detecting whether one of the redundant columns is addressed; should one of the redundant columns be found to be addressed, proceeding with charging of the bit line of the redundant column addressed and interrupting charging of the bit lines of the redundant columns not addressed; and should none of the redundant columns be found to be addressed, interrupting charging of all the bit lines.Type: GrantFiled: April 13, 2000Date of Patent: October 30, 2001Assignee: STMicroelectronics S.r.l.Inventors: Carmelo Condemi, Michele La Placa, Ignazio Martines
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Patent number: 6243310Abstract: An equalization control circuit having an equalization signal generating stage having an enabling input receiving an address transition signal, a disabling input receiving a disabling signal, and an output generating an equalization control signal. An auxiliary line is supplied at one initial terminal (35a) with a biasing voltage correlated to the reading voltage supplied to the addressed array cell. An equalization filter is connected to the end terminal of the auxiliary line and generates the disabling signal when the voltage at the end terminal of the auxiliary line exceeds a preset threshold value.Type: GrantFiled: April 11, 2000Date of Patent: June 5, 2001Assignee: STMicroelectronics S.r.l.Inventors: Carmelo Condemi, Michele La Placa, Ignazio Martines