Patents by Inventor Carmelo Magro

Carmelo Magro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • MOS transistors having vertical current flow
    Patent number: 6093948
    Abstract: The process provides first for the accomplishment of low-doping body regions at the sides and under a gate region and then the accomplishment of high-doping body regions inside said low-doping body regions and self-aligned with said gate region. There is thus obtained an MOS power transistor with vertical current flow which has high-doping body regions self-aligned with said gate region and with a reduced junction depth.
    Type: Grant
    Filed: August 5, 1994
    Date of Patent: July 25, 2000
    Assignees: Consorzio per la Ricerca Sulle Microelettronica nel Mezzogiorno, STMicroelectronics, s.r.l.
    Inventors: Raffaele Zambrano, Carmelo Magro
  • Method for forming MOS transistors having vertical current flow and resulting structure
    Patent number: 5382538
    Abstract: The process provides first for the accomplishment of low-doping body regions at the sides and under a gate region and then the accomplishment of high-doping body regions inside said low-doping body regions and self-aligned with said gate region. There is thus obtained an MOS power transistor with vertical current flow which has high-doping body regions self-aligned with said gate region and with a reduced junction depth.
    Type: Grant
    Filed: May 21, 1993
    Date of Patent: January 17, 1995
    Assignees: Consorzio per la Ricerca Sulla Microelectronica nel, SGS-Thomson Microelectronics S.R.L.
    Inventors: Raffaele Zambrano, Carmelo Magro
  • Metal-semiconductor ohmic contact forming process
    Patent number: 5302549
    Abstract: A metal semiconductor ohmic contact farming process consists of enrichment of the surface of the semiconductor on which contact is to be formed, by ion implantation of a dopant, followed by deposition of a metal film on the implanted surface and then by thermal annealing at a temperature lower than 500.degree. C. and for a period shorter than 60 minutes.
    Type: Grant
    Filed: October 13, 1992
    Date of Patent: April 12, 1994
    Assignee: SGS-Thompson Microelectronics S.r.L.
    Inventors: Antonello Santangelo, Carmelo Magro, Guiseppe Ferla, Paolo Lanza
  • Process for the manufacture of power-MOS semiconductor devices
    Patent number: 5141883
    Abstract: A process for the manufacture of power-MOS semiconductor devices achieves high cell density by the use of self-aligning techniques and photographic exposure equipment of the stepper type. The process calls for definition and formation of the source by a complementary spacer technique and metallization of the source and gate contact areas by silicides after formation of spacers on the gate wall.
    Type: Grant
    Filed: December 24, 1990
    Date of Patent: August 25, 1992
    Assignee: SGS-Thomson Microelectronics S.r.L.
    Inventors: Giuseppe Ferla, Carmelo Magro, Paolo Lanza
  • Process for defining and forming an active region of very limited dimensions in a semiconductor layer
    Patent number: 5130272
    Abstract: Along the outline of a first doped region, a first mask is formed. The mask is made up of a dielectric opposed to the oxygen diffusion. Another mask is created within this first mask, using a process of selective thermal oxidation. The second mask is used to implant dopant in a second region which will only be defined along the outlines of the first region.
    Type: Grant
    Filed: July 9, 1991
    Date of Patent: July 14, 1992
    Assignee: SGS-Thomson Microelectronics S.r.L.
    Inventors: Giuseppe Ferla, Paolo Lanza, Carmelo Magro
  • Method of preventing superficial electrical discharges in chips of semiconductor devices during testing
    Patent number: 4902632
    Abstract: The method consists of subjecting the semiconductor chips to chemical treatment with a silanizing agent immediately before testing to prevent superficial electrical discharges which can reduce the testing voltage which can be applied.
    Type: Grant
    Filed: December 21, 1988
    Date of Patent: February 20, 1990
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventors: Carmelo Oliveri, Carmelo Magro