Abstract: The disclosure relates to an integrator circuit for a Sigma-Delta, ??, modulator, the integrator circuit comprising an integrator module comprising a differential amplifier, a sampling module comprising sampling capacitors and a reference module comprising first and second pluralities of reference capacitors connected between respective first and second lines and first and second pluralities of reference switches for connecting each of the reference capacitors to either a first reference terminal or a second reference terminal. In operation, the reference switches are switched according to a thermometrically coded quantizer signal.

Abstract: The disclosure relates to an integrator circuit (300) for a Sigma-Delta, ??, modulator, the integrator circuit (300) comprising an integrator module (310) comprising a differential amplifier (301), a sampling module (320) comprising sampling capacitors (CS1p, CS2p, CS1n, CS2n) and a reference module (330) comprising first and second pluralities of reference capacitors (3311-x, 3321-x) connected between respective first and second lines (308, 309) and first and second pluralities of reference switches (3311-x, 3321-x) for connecting each of the reference capacitors (3311-x, 3321-x) to either a first reference terminal (324) or a second reference terminal (325). In operation, the reference switches (3311-x, 3321-x) are switched according to a thermometrically coded quantizer signal.

Abstract: The disclosure relates to improvements in bidirectional power switch circuits. Example embodiments include a bidirectional power switch, BPS, circuit (200) comprising: first and second terminals (203, 204); first and second MOSFETs (201, 202, 501, 502) connected in series between the first and second terminals (203, 204) and comprising respective first and second source to body diodes (Dsb, Dsb1, Dsb2); first and second power supply rails (VDD, VEE); first, second, third, fourth and fifth switchable current sources (IDD1-3, SD1-3, IEE1-2, SE1-2); first and second resistors (Rbs, Rgs); and a BPS switching controller (206) configured to control operation of the BPS circuit (200) between a BPS ON state in which the first and second terminals (203, 204) are connected and a BPS OFF state in which the first and second terminals (203, 204) are disconnected.

Abstract: The present disclosure relates to a high voltage bidirectional power switch circuit that includes a high voltage block coupled to a first terminal; and a resistance network including modules connected in parallel with each other between the high voltage block and a second terminal. Each module includes a precision resistor connected in series with a conduction channel of a resistance switching transistor; a first biasing resistor connected between a first conduction channel terminal and a control terminal of the resistance switching transistor; a second biasing resistor connected between a second conduction channel terminal and the control terminal; a body bias control circuit configured to control a bias of body diodes of the resistance switching transistor; a switchable sourcing current source; and a switchable sinking current source. Switches of the switchable sourcing current source and the switchable sinking current source receive switching signals to control the resistance switching transistor.

Abstract: The disclosure relates to improvements in bidirectional power switch circuits. Example embodiments include a bidirectional power switch, BPS, circuit (200) comprising: first and second terminals (203, 204); first and second MOSFETs (201, 202, 501, 502) connected in series between the first and second terminals (203, 204) and comprising respective first and second source to body diodes (Dsb, Dsb1, Dsb2); first and second power supply rails (VDD, VEE); first, second, third, fourth and fifth switchable current sources (IDD1-3, SD1-3, IEE1-2, SE1-2); first and second resistors (Rbs, Rgs); and a BPS switching controller (206) configured to control operation of the BPS circuit (200) between a BPS ON state in which the first and second terminals (203, 204) are connected and a BPS OFF state in which the first and second terminals (203, 204) are disconnected.

Abstract: A high-voltage, HV, bidirectional-power-switch, BPS, circuit comprising: a HV-block coupled to a first-terminal and comprising two HV transistors arranged in series in a BPS configuration; and a resistance-network comprising a plurality of switchable-resistance-modules connected in parallel with each other between the HV-block and a second-terminal, wherein each switchable-resistance-module comprises: a precision-resistor connected in series with a conduction-channel of a resistance-switching-transistor; a first-biasing-resistor connected between a first-conduction-channel-terminal and a control-terminal of the resistance-switching-transistor; a second-biasing-resistor connected between a second-conduction-channel-terminal and the control-terminal of the resistance-switching-transistor; a body-bias-control-circuit configured to control a bias of body diodes of the resistance-switching-transistor; a switchable-sourcing-current-source comprising a first-current-source and a first-source-switch connected in seri

Abstract: One example discloses a reconfigurable analog to digital converter (ADC) device, including: an analog front end (AFE) configured to receive a set of analog input signals and generate a corresponding set of digital output signals; wherein the AFE includes a set of reconfigurable ADC conversion circuits; and a sequencer coupled to the AFE and configured to control the set of reconfigurable ADC conversion circuits with a first AFE channel configuration at a first time and a second AFE channel configuration at a second time.

Abstract: An integrated circuit includes a multiplexer circuit configured to provide an output signal on a conductive line, a programmable gain amplifier having a non-inverting input connected to the conductive line to receive the output signal from the multiplexer, a slew rate adjust circuit connected at a first node on the conductive line between the multiplexer circuit and the programmable gain amplifier, a first switch including a first terminal connected to the first node and a second terminal connected to the input of the programmable gain amplifier, and a low pass filter connected between the first and second terminals of the first switch.

Abstract: One example discloses a reconfigurable analog to digital converter (ADC) device, including: an analog front end (AFE) configured to receive a set of analog input signals and generate a corresponding set of digital output signals; wherein the AFE includes a set of reconfigurable ADC conversion circuits; and a sequencer coupled to the AFE and configured to control the set of reconfigurable ADC conversion circuits with a first AFE channel configuration at a first time and a second AFE channel configuration at a second time.

Abstract: An integrated circuit includes a multiplexer circuit configured to provide an output signal on a conductive line, a programmable gain amplifier having a non-inverting input connected to the conductive line to receive the output signal from the multiplexer, a slew rate adjust circuit connected at a first node on the conductive line between the multiplexer circuit and the programmable gain amplifier, a first switch including a first terminal connected to the first node and a second terminal connected to the input of the programmable gain amplifier, and a low pass filter connected between the first and second terminals of the first switch.

Abstract: A method for quickly shutting down a transistor in a switching circuit includes (a) generating a feedback signal associated with current flowing through the transistor, (b) transmitting the feedback signal through an isolating device to a controller, (c) detecting an over-current condition in the switching circuit without transmitting information through the isolating device, and (d) shutting-down the transistor in response to detecting the over-current condition, without transmitting information through the isolating device.