Patents by Inventor Carminantonio Manganelli
Carminantonio Manganelli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11972294Abstract: A variety of applications can include systems and methods that control a memory size of a changelog in a storage device, where the changelog is implemented to correlate virtual page addresses to physical addresses in one or more memory devices. The memory size can be controlled by an allocation schema for a scalable memory area for the changelog in the storage device. The allocation schema can include using bitmaps, lists linked to the bitmaps, and a counter to count bits asserted in the bitmaps such that the allocation of memory space in the storage device can depend on usage rather than allocating a large memory space for all possible correlations of virtual page addresses to physical addresses.Type: GrantFiled: October 7, 2022Date of Patent: April 30, 2024Assignee: Micron Technology, Inc.Inventors: Angelo Della Monica, Paolo Papa, Carminantonio Manganelli, Massimo Iaculo
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Patent number: 11955189Abstract: Disclosed in some examples are improvements to data placement architectures in NAND that provide additional data protection through an improved NAND data placement schema that allows for recovery from certain failure scenarios. The present disclosure stripes data diagonally across page lines and planes to enhance the data protection. Parity bits are stored in SLC blocks for extra protection until the block is finished writing and then the parity bits may be deleted.Type: GrantFiled: December 5, 2022Date of Patent: April 9, 2024Assignee: Micron Technology, Inc.Inventors: Carminantonio Manganelli, Paolo Papa, Massimo Iaculo, Giuseppe D'Eliseo, Alberto Sassara
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Publication number: 20240112745Abstract: Disclosed in some examples are improvements to data placement architectures in NAND that provide additional data protection through an improved NAND data placement schema that allows for recovery from certain failure scenarios. The present disclosure stripes data diagonally across page lines and planes to enhance the data protection. Parity bits are stored in SLC blocks for extra protection until the block is finished writing and then the parity bits may be deleted.Type: ApplicationFiled: December 4, 2023Publication date: April 4, 2024Inventors: Carminantonio Manganelli, Paolo Papa, Massimo Iaculo, Giuseppe D'Eliseo, Alberto Sassara
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Publication number: 20240061615Abstract: Methods, systems, and devices for command scheduling for a memory system are described. A memory system may be configured to analyze a received command during an initialization procedure for one or more components. In some examples, the memory system may initialize an interface and one or more processing elements as part of an initialization procedure upon transitioning from a first power mode to a second power mode. Accordingly, the command may be analyzed while the processing elements are being initialized such that, upon the processing elements being fully initialized, the command may be processed (e.g., executed).Type: ApplicationFiled: August 22, 2022Publication date: February 22, 2024Inventors: Domenico Francesco De Angelis, Crescenzo Attanasio, Carminantonio Manganelli
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Patent number: 11907556Abstract: Methods, systems, and devices for data relocation operation techniques are described. A memory system may include blocks of memory cells, for example, within a non-volatile memory device of the memory system. The memory system may identify a command to perform a data relocation operation associated with a block of memory cells and may select between a first procedure and a second procedure for performing the data relocation operation. The memory system may select between the first procedure and the second procedure based on whether one or more parameters associated with the data relocation operation satisfy a threshold. For example, the memory system may select the first procedure if the one or more parameters satisfy the threshold and may select the second procedure if the one or more parameters do not satisfy the threshold. The memory system may perform the data relocation operation using the selected procedure.Type: GrantFiled: January 20, 2022Date of Patent: February 20, 2024Assignee: Micron Technology, Inc.Inventors: Paolo Papa, Luigi Esposito, Massimo Iaculo, Giuseppe D'Eliseo, Alberto Sassara, Carminantonio Manganelli, Salvatore Del Prete
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Patent number: 11886346Abstract: A memory device includes a memory array configured with a plurality of memory planes, and control logic, operatively coupled with the memory array. The control logic receives, from a requestor, a plurality of cache read commands requesting first data from the memory array spread across the plurality of memory planes and receives, from the requestor, a cache read context switch command and a snap read command requesting second data from one of the plurality of memory planes of the memory array. Responsive to receiving the cache read context switch command, the control logic suspends processing of the plurality of cache read commands and processes the snap read command to read the second data from the memory array and return the second data to the requestor.Type: GrantFiled: April 22, 2021Date of Patent: January 30, 2024Assignee: Micron Technology, Inc.Inventors: Giuseppe D'Eliseo, Anna Scalesse, Umberto Siciliani, Carminantonio Manganelli
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Patent number: 11869606Abstract: Disclosed in some examples are improvements to data placement architectures in NAND that provide additional data protection through an improved NAND data placement schema that allows for recovery from certain failure scenarios. The present disclosure stripes data diagonally across page lines and planes to enhance the data protection. Parity bits are stored in SLC blocks for extra protection until the block is finished writing and then the parity bits may be deleted.Type: GrantFiled: December 5, 2022Date of Patent: January 9, 2024Assignee: Micron Technology, Inc.Inventors: Carminantonio Manganelli, Paolo Papa, Massimo Iaculo, Giuseppe D'Eliseo, Alberto Sassara
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Publication number: 20230367478Abstract: Disclosed in some examples are improvements to data placement architectures in NAND that provide additional data protection through an improved NAND data placement schema that allows for recovery from certain failure scenarios. The present disclosure stripes data diagonally across page lines and planes to enhance the data protection. Parity bits are stored in SLC blocks for extra protection until the block is finished writing and then the parity bits may be deleted.Type: ApplicationFiled: April 21, 2023Publication date: November 16, 2023Inventors: Paolo Papa, Carminantonio Manganelli, Massimo Iaculo, Giuseppe D'Eliseo, Alberto Sassara
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Patent number: 11675709Abstract: In one approach, a computer storage device has one or more pivot tables and corresponding bit maps stored in volatile memory. The storage device has non-volatile storage media that stores data for a host device. The pivot tables and bit maps are used to determine physical addresses of the non-volatile storage media for logical addresses received in commands from the host device that are determined to be within a sequential address range (e.g., LBAs that are part of a prior sequential write operation by the host device). When a command is received by the storage device that includes a logical address within the sequential address range, then one of the pivot tables and its corresponding bit map are used to determine the physical address of the non-volatile storage media that corresponds to the logical address.Type: GrantFiled: October 5, 2021Date of Patent: June 13, 2023Assignee: Micron Technology, Inc.Inventors: Giuseppe D'Eliseo, Carminantonio Manganelli, Paolo Papa, Yoav Weinberg, Giuseppe Ferrari, Massimo Iaculo, Lalla Fatima Drissi
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Patent number: 11650931Abstract: A variety of applications can include systems and methods that utilize a hybrid logical to physical (L2P) caching scheme. A L2P cache and a L2P changelog in a storage device can be controlled for use in write and read operations of a memory system. A page pointer table in the L2P cache can be accessed, for performance of a write operation in the memory system, to obtain a specific physical address mapped to a specified logical block address from a host, where the access is based on the page pointer table loaded into the L2P cache from the L2P changelog. The L2P cache area can be progressively configured with the most frequently accessed page pointer tables in the L2P changelog in the latest host accesses.Type: GrantFiled: April 19, 2021Date of Patent: May 16, 2023Assignee: Micron Technology, Inc.Inventors: Carminantonio Manganelli, Yoav Weinberg, Alberto Sassara, Paolo Papa, Luigi Esposito, Giuseppe D'Eliseo, Angelo Della Monica, Massimo Iaculo
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Patent number: 11635894Abstract: Disclosed in some examples are improvements to data placement architectures in NAND that provide additional data protection through an improved NAND data placement schema that allows for recovery from certain failure scenarios. The present disclosure stripes data diagonally across page lines and planes to enhance the data protection. Parity bits are stored in SLC blocks for extra protection until the block is finished writing and then the parity bits may be deleted.Type: GrantFiled: March 15, 2019Date of Patent: April 25, 2023Assignee: Micron Technology, Inc.Inventors: Paolo Papa, Carminantonio Manganelli, Massimo Iaculo, Giuseppe D'Eliseo, Alberto Sassara
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Publication number: 20230100916Abstract: Disclosed in some examples are improvements to data placement architectures in NAND that provide additional data protection through an improved NAND data placement schema that allows for recovery from certain failure scenarios. The present disclosure stripes data diagonally across page lines and planes to enhance the data protection. Parity bits are stored in SLC blocks for extra protection until the block is finished writing and then the parity bits may be deleted.Type: ApplicationFiled: December 5, 2022Publication date: March 30, 2023Inventors: Carminantonio Manganelli, Paolp Papa, Massimo Iaculo, Giuseppe D'Eliseo, Alberto Sassara
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Publication number: 20230033903Abstract: A variety of applications can include systems and methods that control a memory size of a changelog in a storage device, where the changelog is implemented to correlate virtual page addresses to physical addresses in one or more memory devices. The memory size can be controlled by an allocation schema for a scalable memory area for the changelog in the storage device. The allocation schema can include using bitmaps, lists linked to the bitmaps, and a counter to count bits asserted in the bitmaps such that the allocation of memory space in the storage device can depend on usage rather than allocating a large memory space for all possible correlations of virtual page addresses to physical addresses.Type: ApplicationFiled: October 7, 2022Publication date: February 2, 2023Inventors: Angelo Della Monica, Paolo Papa, Carminantonio Manganelli, Massimo Laculo
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Patent number: 11521690Abstract: Disclosed in some examples are improvements to data placement architectures in NAND that provide additional data protection through an improved NAND data placement schema that allows for recovery from certain failure scenarios. The present disclosure stripes data diagonally across page lines and planes to enhance the data protection. Parity bits are stored in SLC blocks for extra protection until the block is finished writing and then the parity bits may be deleted.Type: GrantFiled: March 15, 2019Date of Patent: December 6, 2022Assignee: Micron Technology, Inc.Inventors: Carminantonio Manganelli, Paolo Papa, Massimo Iaculo, Giuseppe D'Eliseo, Alberto Sassara
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Publication number: 20220342823Abstract: A memory device includes a memory array configured with a plurality of memory planes, and control logic, operatively coupled with the memory array. The control logic receives, from a requestor, a plurality of cache read commands requesting first data from the memory array spread across the plurality of memory planes and receives, from the requestor, a cache read context switch command and a snap read command requesting second data from one of the plurality of memory planes of the memory array. Responsive to receiving the cache read context switch command, the control logic suspends processing of the plurality of cache read commands and processes the snap read command to read the second data from the memory array and return the second data to the requestor.Type: ApplicationFiled: April 22, 2021Publication date: October 27, 2022Inventors: Giuseppe D'Eliseo, Anna Scalesse, Umberto Siciliani, Carminantonio Manganelli
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Patent number: 11474865Abstract: A variety of applications can include systems and methods that control a memory size of a changelog in a storage device, where the changelog is implemented to correlate virtual page addresses to physical addresses in one or more memory devices. The memory size can be controlled by an allocation schema for a scalable memory area for the changelog in the storage device. The allocation schema can include using bitmaps, lists linked to the bitmaps, and a counter to count bits asserted in the bitmaps such that the allocation of memory space in the storage device can depend on usage rather than allocating a large memory space for all possible correlations of virtual page addresses to physical addresses.Type: GrantFiled: August 23, 2019Date of Patent: October 18, 2022Assignee: Micron Technology, Inc.Inventors: Angelo Della Monica, Paolo Papa, Carminantonio Manganelli, Massimo Iaculo
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Publication number: 20220261153Abstract: Methods, systems, and devices for data relocation operation techniques are described. A memory system may include blocks of memory cells, for example, within a non-volatile memory device of the memory system. The memory system may identify a command to perform a data relocation operation associated with a block of memory cells and may select between a first procedure and a second procedure for performing the data relocation operation. The memory system may select between the first procedure and the second procedure based on whether one or more parameters associated with the data relocation operation satisfy a threshold. For example, the memory system may select the first procedure if the one or more parameters satisfy the threshold and may select the second procedure if the one or more parameters do not satisfy the threshold. The memory system may perform the data relocation operation using the selected procedure.Type: ApplicationFiled: January 20, 2022Publication date: August 18, 2022Inventors: Paolo Papa, Luigi Esposito, Massimo Iaculo, Giuseppe D'Eliseo, Alberto Sassara, Carminantonio Manganelli, Salvatore Del Prete
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Publication number: 20220237080Abstract: Methods, systems, and devices for device fault condition reporting are described. A host system may transmit, to a memory system, a command to perform an operation. The memory system may receive the command and identify a fault condition associated with performing the operation. The memory system may transmit, to the host system, a message that indicates the fault condition. After the memory system transmits the message, the memory system may enter a safe mode of operation based on identifying the fault condition.Type: ApplicationFiled: December 20, 2021Publication date: July 28, 2022Inventors: Crescenzo Attanasio, Carminantonio Manganelli, Massimo Iaculo, Paolo Papa, Antonio Eliso
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Publication number: 20220027284Abstract: In one approach, a computer storage device has one or more pivot tables and corresponding bit maps stored in volatile memory. The storage device has non-volatile storage media that stores data for a host device. The pivot tables and bit maps are used to determine physical addresses of the non-volatile storage media for logical addresses received in commands from the host device that are determined to be within a sequential address range (e.g., LBAs that are part of a prior sequential write operation by the host device). When a command is received by the storage device that includes a logical address within the sequential address range, then one of the pivot tables and its corresponding bit map are used to determine the physical address of the non-volatile storage media that corresponds to the logical address.Type: ApplicationFiled: October 5, 2021Publication date: January 27, 2022Inventors: Giuseppe D'Eliseo, Carminantonio Manganelli, Paolo Papa, Yoav Weinberg, Giuseppe Ferrari, Massimo Iaculo, Lalla Fatima Drissi
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Publication number: 20210357127Abstract: Disclosed in some examples are improvements to data placement architectures in NAND that provide additional data protection through an improved NAND data placement schema that allows for recovery from certain failure scenarios. The present disclosure stripes data diagonally across page lines and planes to enhance the data protection. Parity bits are stored in SLC blocks for extra protection until the block is finished writing and then the parity bits may be deleted.Type: ApplicationFiled: March 15, 2019Publication date: November 18, 2021Inventors: Paolo Papa, Carminantonio Manganelli, Massimo Iaculo, Giuseppe D'Eliseo, Alberto Sassara