Abstract: A system and method for developing a reusable electronic circuit design module are presented in various embodiments. In one embodiment, the functional design elements comprising a design module are entered into a database along with documentation elements that describe the design elements. The functional design elements are linked with selected ones of the documentation elements in the database. A testbench is simulated with the design module, and the generated results are stored in a database and linked with the functional design elements. By linking the simulation results, documentation, and design elements, the characteristics of the design module are easily ascertained by a designer who is reusing the design module.

Abstract: A method and apparatus for analyzing performance and density of a source design module for a target programmable gate array. The source design module is converted to logic for a selected target programmable gate array. Performance and density of the converted logic are then estimated. If the estimated performance level does not achieve a target performance level, then problematic design elements are automatically or optionally converted to functionally equivalent programmable gate array design elements. The performance and density of the target programmable gate array is again estimated using the new design elements. In another mode of operation, design guidance is provided in converting the problematic design elements.

Abstract: The notion of global signals (e.g., global set/reset and global tristate) is of significance to programmable logic user throughout the design process. Regardless of whether the HDL designer explicitly describes the use of a global signal, they are present in the implemented device since they are an integral part of the initialization and start-up process. This may lead to mismatches between the Register Transfer Level (RTL) simulation and the timing simulation. While a methodology for verifying the functionality of global signals is available for schematic design entry, none exists for HDL design tools. A verification method for HDL designers is disclosed providing access to all the functionality relating to global networks currently available to the schematic designers and allowing reuse of the testbench without losing HDL code portability.