Abstract: A delay locked loop (DLL) circuit having gain control is presented. The DLL circuit includes a bias generator responsive based on an error signal to produce first and second bias voltages to control a plurality of differential delay elements. The bias generator includes a bias current generator having a fixed voltage-controlled current source and a dynamic voltage-controlled current source to generate a bias current, and a bias voltage generator for receiving the bias current and generating first and second bias voltages. The bias generator can generate multiple current levels in different modes of operation. Each of the current levels of the bias generator allows a small range of currents and therefore small values of gain factors (KVCDL). Low KVCDL values leads to lower jitter and better control over feedback stability, resulting in an increase in the range of operational frequencies.

Abstract: A phase locked loop (PLL) circuit adjusts a voltage controlled differential oscillator to generate an output frequency signal that is a selected multiple of an input reference signal. An oscillator control circuit increases and decreases the output frequency signal. A frequency detector detects a phase shift between the reference signal and the PLL output signal and produces an error signal. In response to the error signal, a fast lock circuit detects when the output frequency signal passes the selected multiple of the reference signal.

Abstract: A delay locked loop (DLL) circuit having gain control is presented. The DLL circuit includes a bias generator responsive based on an error signal to produce first and second bias voltages to control a plurality of differential delay elements. The bias generator includes a bias current generator having a fixed voltage-controlled current source and a dynamic voltage-controlled current source to generate a bias current, and a bias voltage generator for receiving the bias current and generating first and second bias voltages. The bias generator can generate multiple current levels in different modes of operation. Each of the current levels of the bias generator allows a small range of currents and therefore small values of gain factors (KVCDL). Low KVCDL values leads to lower jitter and better control over feedback stability, resulting in an increase in the range of operational frequencies.

Abstract: A phase locked loop (PLL) circuit adjusts a voltage controlled differential oscillator to generate an output frequency signal that is a selected multiple of an input reference signal. An oscillator control circuit increases and decreases the output frequency signal. A frequency detector detects a phase shift between the reference signal and the PLL output signal and produces an error signal. In response to the error signal, a fast lock circuit detects when the output frequency signal passes the selected multiple of the reference signal.

Abstract: A phase locked loop (PLL) circuit adjusts a voltage controlled differential oscillator to generate an output frequency signal, which is a selected multiple of an input reference signal. The PLL circuit includes an oscillator control circuit for increasing and decreasing the PLL output frequency signal, a frequency detector for detecting a phase shift between the reference signal and the PLL output signal and produces an error signal, and a fast lock circuit for detecting when the output frequency signal passes the selected multiple of the reference signal. This circuit design provides improved jitter performance, tolerates process variation, and extends the PLL operating frequency range.

Abstract: A content addressable memory (CAM) has a CAM array and a CAM encoder. The CAM array in response to data stored in a memory address of the CAM array matching comparison data, produces a match signal corresponding to the memory address. The CAM encoder receives the match signal and using encoded cells, produces the memory address corresponding to the match signal.

Abstract: A phase locked loop (PLL) circuit adjusts a voltage controlled differential oscillator to generate an output frequency signal, which is a selected multiple of an input reference signal. The PLL circuit includes an oscillator control circuit for increasing and decreasing the PLL output frequency signal, a frequency detector for detecting a phase shift between the reference signal and the PLL output signal and produces an error signal, and a fast lock circuit for detecting when the output frequency signal passes the selected multiple of the reference signal. This circuit design provides improved jitter performance, tolerates process variation, and extends the PLL operating frequency range.

Abstract: An input buffer circuit is disclosed. The circuit has a single stage circuit portion for receiving a multiplexed row address bit and a multiplexed column address bit. Circuitry is connected to the single stage circuit portion for separately holding the received multiplexed row address bit and the received multiplexed column address bit. The single stage circuit portion may include a tri-state inverter having a tri-state control input coupled to an input buffer control signal and a latch to hold the output of the tri-state inverter when it is tri-stated by the input buffer control signal. The first circuit portion may be of the CMOS type. Such a circuit is useful in the memory support circuitry of an integrated circuit of the dynamic random access memory type.