Patents by Inventor Carol M. Gelatos

Carol M. Gelatos has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device, memory cell, and processes for forming them
    Patent number: 6686633
    Abstract: A semiconductor device includes a memory array of static-random-access memory cells. The SRAM cells are formed using a process flow more closely associated with logic-type devices. The SRAM cells are formed using one semiconductor layer compared to at least three typically seen with SRAM cells. The SRAM cells include many features that allow its dimensions to be scaled to very small dimensions (less than 0.25 microns and possible down to 0.1 microns or even smaller). A unique process integration scheme allows formation of local interconnects (522 and 524), wherein each local interconnect (522, 524) cross couples the inverters of the SRAM and is formed within a single opening (70). Also, interconnect portions (104) of word lines are laterally offset from silicon portions (36) of the same word line, so that the interconnect portions do not interfere with bit line connections.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: February 3, 2004
    Assignee: Motorola, Inc.
    Inventors: Craig S. Lage, Mousumi Bhat, Yeong-Jyh Tom Lii, Andrew G. Nagy, Larry E. Frisa, Stanley M. Filipiak, David L. O'Meara, T. P. Ong, Michael P. Woo, Terry G. Sparks, Carol M. Gelatos
  • Process for forming a semiconductor device having an interconnect or conductive film electrically insulated from a conductive member or region
    Patent number: 6184073
    Abstract: A semiconductor device includes a memory array of static-random-access memory cells. The SRAM cells are formed using a process flow more closely associated with logic-type devices. The SRAM cells are formed using one semiconductor layer compared to at least three typically seen with SRAM cells. The SRAM cells include many features that allow its dimensions to be scaled to very small dimensions (less than 0.25 microns and possible down to 0.1 microns or even smaller). A unique process integration scheme allows formation of local interconnects (522 and 524), wherein each local interconnect (522, 524) cross couples the inverters of the SRAM and is formed within a single opening (70). Also, interconnect portions (104) of word lines are laterally offset from silicon portions (36) of the same word line, so that the interconnect portions do not interfere with bit line connections.
    Type: Grant
    Filed: December 23, 1997
    Date of Patent: February 6, 2001
    Assignee: Motorola, Inc.
    Inventors: Craig S. Lage, Mousumi Bhat, Yeong-Jyh Tom Lii, Andrew G. Nagy, Larry E. Frisa, Stanley M. Filipiak, David L. O'Meara, T. P. Ong, Michael P. Woo, Terry G. Sparks, Carol M. Gelatos