Patents by Inventor Carol Namba

Carol Namba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of forming a high electron mobility transistor hemt, utilizing self-aligned miniature field mitigating plate and protective dielectric layer
    Patent number: 7897446
    Abstract: A semiconductor device is fabricated to include source and drain contacts including an ohmic metal sunken into the barrier layer and a portion of the channel layer; a protective dielectric layer disposed between the source and drain contacts on the barrier layer; a metallization layer disposed in drain and source ohmic vias between the source contact and the protective dielectric layer and between the protective dielectric layer and the drain contact; and a metal T-gate disposed above the barrier layer including a field mitigating plate disposed on a side portion of a stem of the metal T-gate.
    Type: Grant
    Filed: March 25, 2010
    Date of Patent: March 1, 2011
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Ioulia Smorchkova, Robert Coffie, Ben Heying, Carol Namba, Po-Hsin Liu, Boris Hikin
  • High electron mobility transistor semiconductor device having field mitigating plate and fabrication method thereof
    Patent number: 7800132
    Abstract: A semiconductor device includes a T-gate disposed between drain and source regions and above a barrier layer to form a Schottky contact to the channel layer. A first inactive field mitigating plate is disposed above a portion of the T-gate and a second active field plate is disposed above the barrier layer and in a vicinity of the T-gate.
    Type: Grant
    Filed: October 25, 2007
    Date of Patent: September 21, 2010
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Ioulia Smorchkova, Carol Namba, Po-Hsin Liu, Robert Coffie, Roger Tsai
  • High electron mobility transistor having self-aligned miniature field mitigating plate and protective dielectric layer and fabrication method thereof
    Publication number: 20100184262
    Abstract: A semiconductor device is fabricated to include source and drain contacts including an ohmic metal sunken into the barrier layer and a portion of the channel layer; a protective dielectric layer disposed between the source and drain contacts on the barrier layer; a metallization layer disposed in drain and source ohmic vias between the source contact and the protective dielectric layer and between the protective dielectric layer and the drain contact; and a metal T-gate disposed above the barrier layer including a field mitigating plate disposed on a side portion of a stem of the metal T-gate.
    Type: Application
    Filed: March 25, 2010
    Publication date: July 22, 2010
    Applicant: Northrop Grumman Space and Mission Systems Corp.
    Inventors: Ioulia Smorchkova, Robert Coffie, Ben Heying, Carol Namba, Po-Hsin Liu, Boris Hikin
  • High electron mobility transistor having self-aligned miniature field mitigating plate on a protective dielectric layer
    Patent number: 7750370
    Abstract: A semiconductor device is fabricated to include source and drain contacts including an ohmic metal sunken into the barrier layer and a portion of the channel layer; a protective dielectric layer disposed between the source and drain contacts on the barrier layer; a metallization layer disposed in drain and source ohmic vias between the source contact and the protective dielectric layer and between the protective dielectric layer and the drain contact; and a metal T-gate disposed above the barrier layer including a field mitigating plate disposed on a side portion of a stem of the metal T-gate.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: July 6, 2010
    Assignee: Northrop Grumman Space & Mission Systems Corp.
    Inventors: Ioulia Smorchkova, Robert Coffie, Ben Heying, Carol Namba, Po-Hsin Liu, Boris Hikin
  • High electron mobility transistor having self-aligned miniature field mitigating plate and protective dielectric layer and fabrication method thereof
    Publication number: 20090159930
    Abstract: A semiconductor device is fabricated to include source and drain contacts including an ohmic metal sunken into the barrier layer and a portion of the channel layer; a protective dielectric layer disposed between the source and drain contacts on the barrier layer; a metallization layer disposed in drain and source ohmic vias between the source contact and the protective dielectric layer and between the protective dielectric layer and the drain contact; and a metal T-gate disposed above the barrier layer including a field mitigating plate disposed on a side portion of a stem of the metal T-gate.
    Type: Application
    Filed: December 20, 2007
    Publication date: June 25, 2009
    Applicant: Northrop Grumman Space and Mission System Corp.
    Inventors: loulia Smorchkova, Robert Coffie, Ben Heying, Carol Namba, Po-Hsin Liu, Boris Hikin
  • High electron mobility transistor semiconductor device having field mitigating plate and fabrication method thereof
    Publication number: 20090108299
    Abstract: A semiconductor device includes a T-gate disposed between drain and source regions and above a barrier layer to form a Schottky contact to the channel layer. A first inactive field mitigating plate is disposed above a portion of the T-gate and a second active field plate is disposed above the barrier layer and in a vicinity of the T-gate.
    Type: Application
    Filed: October 25, 2007
    Publication date: April 30, 2009
    Applicant: Northrop Grumman Space and Mission Systems Corp.
    Inventors: Ioulia Smorchkova, Carol Namba, Po-Hsin Liu, Robert Coffie, Roger Tsai