Abstract: An apparatus and method for distinguishing correctable bit errors in memory. A bit error detection module detects a correctable bit error in a memory in response to a READ operation. The correctable bit error is correctable using error-correcting code. The READ operation is generated during normal operation. A comparison module compares an error location indicator with a stored error location indicator. The error location indicator includes a memory location of the correctable bit error. The stored error location indicator corresponds to a previously stored error location indicator of a previous correctable bit error. A storage module stores the error location indicator if the comparison module determines that the error location indicator differs from a stored error location indicator. An error counter module increases an error counter corresponding to the error location indicator if the comparison module determines that the error location indicator matches a stored error location indicator.

Abstract: Provided are a method, system, and program for an adaptor to read and write to system memory. A plurality of blocks of data to write to storage are received at an adaptor. The blocks of data are added to a buffer in the adaptor. A determination is made of pages in a memory device and I/O requests are generated to write the blocks in the buffer to the determined pages, wherein two I/O requests are generated to write to one block split between two pages in the memory device. The adaptor executes the generated I/O requests to write the blocks in the buffer to the determined pages in the memory device.

Abstract: An apparatus, system, and method are disclosed for distinguishing correctable bit errors in memory. A bit error detection module detects a correctable bit error in memory. The correctable bit error is correctable using error-correcting code (“ECC”). A comparison module compares an error location indicator with a stored error location indicator. The error location indicator is a location of the correctable bit error. The stored error location indicator includes to at least one previously stored error location indicator of a previously detected correctable bit error. A storage module stores the error location indicator in response to the comparison module determining that the error location indicator differs from a stored error location indicator. A bit error counter module increases a random bit error counter if the comparison module determines that the error location indicator differs from a stored error location indicator and does not increase the random bit error counter otherwise.

Abstract: An apparatus, system, and method are disclosed for adapter card failover. A switch module connects a first processor complex to an adapter card through a first port as an owner processor complex. The owner processor complex manages the adapter card except for a second port and receives error messages from the adapter card. The switch module further connects a second processor complex to the adapter card through the second port as a non-owner processor complex. The non-owner processor complex manages the second port. A detection module detects a failure of the first processor complex. A setup module modifies the switch module to logically connect the second processor complex to the adapter card as the owner processor complex and to logically disconnect the first processor complex from the adapter card in response to detecting the failure.

Abstract: A method, apparatus and program storage device for performing a self-healing cache process is described. At least one error affecting a cache is detected. The cache may have a matching address tag for a fetching operation. Based on the type of error, a self-healing cache process is performed based.

Abstract: Provided are a method, system, and program for an adaptor to read and write to system memory. A plurality of blocks of data to write to storage are received at an adaptor. The blocks of data are added to a buffer in the adaptor. A determination is made of pages in a memory device and I/O requests are generated to write the blocks in the buffer to the determined pages, wherein two I/O requests are generated to write to one block split between two pages in the memory device. The adaptor executes the generated I/O requests to write the blocks in the buffer to the determined pages in the memory device.

Abstract: A method, apparatus and program storage device for managing dataflow through a processing system is disclosed. A buffer monitor maintains and monitors a buffer full threshold to control the write throughput to a data bus.

Abstract: Provided are a method, system, and program for an adaptor to read and write to system memory. A plurality of blocks of data to write to storage are received at an adaptor. The blocks of data are added to a buffer in the adaptor. A determination is made of pages in a memory device and I/O requests are generated to write the blocks in the buffer to the determined pages, wherein two I/O requests are generated to write to one block split between two pages in the memory device. The adaptor executes the generated I/O requests to write the blocks in the buffer to the determined pages in the memory device.

Abstract: One embodiment of an adapter card in accordance with the invention includes a circuit board connectable to a motherboard of a computer system. A logic chip is connected to the circuit board to provide functionality to the adapter card. One or more programmable devices are connected to the circuit board and store data read by the logic chip upon initialization. This data may include first character data to program the logic chip to have a first character and second character data to program the logic chip to have a second character. A switching mechanism is provided to switch between the first and second character data in response to an external input, thereby causing the logic chip to read one of the first and second character data.

Abstract: A method, apparatus and program storage device for providing self-quiesced logic for handling an error recovery instruction such as a reset or self-test instruction. For example, during a reset or self test procedure, the logic is isolated without adversely affecting the local processor. Self-quiesced logic processes an error recovery instruction by monitoring the processor interface for an idle condition and withholding access to the local processor. Once the local processor interface has been quiesced and the internal logic paths are idle, the logic will proceed with the reset or self-test.

Abstract: A system and method for recording trace data while conserving cache resources includes generating trace data and creating a cache line containing the trace data. The cache line is assigned a tag which corresponds to an intermediate address designated for processing the trace data. The cache line also contains embedded therein an actual address in memory for storing the trace data, which may include either a real address or a virtual address. The cache line may be received at the intermediate address and parsed to read the actual address. The trace data may then be written to a location in memory corresponding to the actual address. By routing trace data through a designated intermediate address, CPU cache may be conserved for other more important or more frequently accessed data.

Abstract: A method, apparatus and program storage device for managing dataflow through a processing system is disclosed. A buffer monitor maintains and monitors a buffer full threshold to control the write throughput to a data bus.

Abstract: A method, apparatus and program storage device for performing a self-healing cache process is described. At least one error affecting a cache is detected. The cache may have a matching address tag for a fetching operation. Based on the type of error, a self-healing cache process is performed based.

Abstract: One embodiment of an adapter card in accordance with the invention includes a circuit board connectable to a motherboard of a computer system. A logic chip is connected to the circuit board to provide functionality to the adapter card. One or more programmable devices are connected to the circuit board and store data read by the logic chip upon initialization. This data may include first character data to program the logic chip to have a first character and second character data to program the logic chip to have a second character. A switching mechanism is provided to switch between the first and second character data in response to an external input, thereby causing the logic chip to read one of the first and second character data.

Abstract: An apparatus, system, and method are disclosed for distinguishing correctable bit errors in memory. A bit error detection module detects a correctable bit error in memory. The correctable bit error is correctable using error-correcting code (“ECC”). A comparison module compares an error location indicator with a stored error location indicator. The error location indicator is a location of the correctable bit error. The stored error location indicator includes to at least one previously stored error location indicator of a previously detected correctable bit error. A storage module stores the error location indicator in response to the comparison module determining that the error location indicator differs from a stored error location indicator. A bit error counter module increases a random bit error counter if the comparison module determines that the error location indicator differs from a stored error location indicator and does not increase the random bit error counter otherwise.

Abstract: An apparatus and method are disclosed for distinguishing correctable bit errors in memory. A bit error detection module detects a correctable bit error in a memory in response to a READ operation. The correctable bit error is correctable using error-correcting code. The READ operation is generated during normal operation. A comparison module compares an error location indicator with a stored error location indicator. The error location indicator includes a memory location of the correctable bit error. The stored error location indicator corresponds to a previously stored error location indicator of a previous correctable bit error. A storage module stores the error location indicator if the comparison module determines that the error location indicator differs from a stored error location indicator. An error counter module increases an error counter corresponding to the error location indicator if the comparison module determines that the error location indicator matches a stored error location indicator.

Abstract: An apparatus, system, and method are disclosed for adapter card failover. A switch module connects a first processor complex to an adapter card through a first port as an owner processor complex. The owner processor complex manages the adapter card except for a second port and receives error messages from the adapter card. The switch module further connects a second processor complex to the adapter card through the second port as a non-owner processor complex. The non-owner processor complex manages the second port. A detection module detects a failure of the first processor complex. A setup module modifies the switch module to logically connect the second processor complex to the adapter card as the owner processor complex and to logically disconnect the first processor complex from the adapter card in response to detecting the failure.

Abstract: An apparatus, system, and method are disclosed for adapter card failover. A switch module connects a first processor complex to an adapter card through a first port as an owner processor complex. The owner processor complex manages the adapter card except for a second port and receives error messages from the adapter card. The switch module further connects a second processor complex to the adapter card through the second port as a non-owner processor complex. The non-owner processor complex manages the second port. A detection module detects a failure of the first processor complex. A setup module modifies the switch module to logically connect the second processor complex to the adapter card as the owner processor complex and to logically disconnect the first processor complex from the adapter card in response to detecting the failure.

Abstract: A method, apparatus and program storage device for performing a self-healing cache process is described. At least one error affecting a cache is detected. The cache may have a matching address tag for a fetching operation. Based on the type of error, a self-healing cache process is performed based.

Abstract: A method, apparatus and program storage device for managing dataflow through a processing system is disclosed. A buffer monitor maintains and monitors a buffer full threshold to control the write throughput to a data bus.