Patents by Inventor Carole Dulong
Carole Dulong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9489716Abstract: A street-level imagery acquisition and selection process identifies which images are published in a street field view. An imagery database includes panoramas each corresponding to a set of images acquired from a single viewpoint. The panoramas are attached to corresponding positions on a road network graph. The graph is divided into a set of selection paths, each of which includes a topologically linear sequence of road segments. Each selection path is evaluated to select a set of panoramas to be published in the path. Panoramas of interior road segments are selected before panoramas at intersections. Selected panorama identifiers for each interior road segment of the selection paths and each intersection correspond to a position along the road network graph. The selected panorama identifiers are then published in the street field view.Type: GrantFiled: April 21, 2015Date of Patent: November 8, 2016Assignee: Google Inc.Inventors: Abhijit S. Ogale, Rodrigo L. Carceroni, Carole Dulong, Luc Vincent
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Patent number: 9036000Abstract: A street-level imagery acquisition and selection process identifies which images are published in a street field view. An imagery database includes panoramas each corresponding to a set of images acquired from a single viewpoint. The panoramas are attached to corresponding positions on a road network graph. The graph is divided into a set of selection paths, each of which includes a topologically linear sequence of road segments. Each selection path is evaluated to select a set of panoramas to be published in the path. Panoramas of interior road segments are selected before panoramas at intersections. Selected panorama identifiers for each interior road segment of the selection paths and each intersection correspond to a position along the road network graph. The selected panorama identifiers are then published in the street field view.Type: GrantFiled: September 27, 2011Date of Patent: May 19, 2015Assignee: Google Inc.Inventors: Abhijit S. Ogale, Rodrigo L. Carceroni, Carole Dulong, Luc Vincent
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Patent number: 8793299Abstract: A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.Type: GrantFiled: March 13, 2013Date of Patent: July 29, 2014Assignee: Intel CorporationInventors: Alexander Peleg, Millind Mittal, Larry M. Mennemeier, Benny Eitan, Carole Dulong, Eiichi Kowashi, Wolf C. Witt
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Patent number: 8745119Abstract: A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.Type: GrantFiled: March 13, 2013Date of Patent: June 3, 2014Assignee: Intel CorporationInventors: Alexander Peleg, Millind Mittal, Larry M. Mennemeier, Benny Eitan, Carole Dulong, Eiichi Kowashi, Wolf C. Witt
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Patent number: 8725787Abstract: A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.Type: GrantFiled: April 26, 2012Date of Patent: May 13, 2014Assignee: Intel CorporationInventors: Alexander D. Peleg, Millind Mittal, Larry M. Mennemeier, Benny Eitan, Carole Dulong, Eiichi Kowashi, Wolf Witt
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Patent number: 8626814Abstract: A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.Type: GrantFiled: July 1, 2011Date of Patent: January 7, 2014Assignee: Intel CorporationInventors: Alexander Peleg, Milland Mittal, Larry M. Mennemeier, Benny Eitan, Carole Dulong, Eiichi Kowashi, Wolf C. Witt
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Patent number: 8565537Abstract: A processing system may receive an example image for use in querying a collection of digital images. The processing system may use local and global feature descriptors to perform a content-based image comparison of the digital images with the example image, to automatically rank the digital images with respect to similarity to the example image. A local feature descriptor may represent a portion of the contents of a digital image. A global feature descriptor may represent substantially all of the contents of that digital image. The global feature descriptor may be content based, not keyword based. Intermediate and final classifiers may be used to perform the automatic ranking. Different intermediate classifiers may generate intermediate relevance metrics with respect to different modalities. The final classifier may use results from the intermediate classifiers to produce a final relevance metric for the digital images. Other embodiments are described and claimed.Type: GrantFiled: March 15, 2012Date of Patent: October 22, 2013Assignee: Intel CorporationInventors: Jean-Yves Bouguet, Carole Dulong, Igor V. Kozintsev, Yi Wu, Ara Nefian
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Publication number: 20130262836Abstract: A method and apparatus for including in a processor instructions for performing multiply-subtract operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-subtract operations on data elements in the first and second packed data.Type: ApplicationFiled: May 30, 2013Publication date: October 3, 2013Inventors: Alexander Peleg, Milland Mittal, Larry M. Mennemeier, Benny Eitan, Carole Dulong, Eiichi Kowashi, Wolf C. Witt
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Publication number: 20130262547Abstract: A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.Type: ApplicationFiled: May 30, 2013Publication date: October 3, 2013Inventors: Alexander Peleg, Milland Mittal, Larry M. Mennemeier, Benny Eitan, Carole Dulong, Eiichi Kowashi, Wolf C. Witt
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Publication number: 20130219151Abstract: A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.Type: ApplicationFiled: March 13, 2013Publication date: August 22, 2013Inventors: Alexander Peleg, Millind Mittal, Larry M. Mennemeier, Benny Eitan, Carole Dulong, Eiichi Kowashi, Wolf C. Witt
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Publication number: 20130198254Abstract: A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.Type: ApplicationFiled: March 13, 2013Publication date: August 1, 2013Inventors: Alexander Peleg, Millind Mittal, Larry M. Mennemeier, Benny Eitan, Carole Dulong, Eiichi Kowashi, Wolf C. Witt
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Patent number: 8495123Abstract: A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.Type: GrantFiled: October 1, 2012Date of Patent: July 23, 2013Assignee: Intel CorporationInventors: Alexander Peleg, Millind Mittal, Larry M. Mennemeier, Benny Eitan, Carole Dulong, Eiichi Kowashi, Wolf C. Witt
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Publication number: 20130091190Abstract: A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.Type: ApplicationFiled: October 1, 2012Publication date: April 11, 2013Applicant: INTEL CORPORATIONInventors: Alexander Peleg, Millind Mittal, Larry M. Mennemeier, Benny Eitan, Carole Dulong, Eiichi Kowashi, Wolf C. Witt
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Patent number: 8396915Abstract: A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.Type: GrantFiled: September 4, 2012Date of Patent: March 12, 2013Assignee: Intel CorporationInventors: Alexander Peleg, Millind Mittal, Larry M. Mennemeier, Benny Eitan, Carole Dulong, Eiichi Kowashi, Wolf C. Witt
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Publication number: 20120331028Abstract: A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.Type: ApplicationFiled: September 4, 2012Publication date: December 27, 2012Inventors: Alexander D. Peleg, Millind Mittal, Larry M. Mennemeier, Benny Eitan, Carole Dulong, Eiichi Kowashi, Wolf Witt
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Publication number: 20120216018Abstract: A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.Type: ApplicationFiled: April 26, 2012Publication date: August 23, 2012Inventors: Alexander D. Peleg, Millind Mittal, Larry M. Mennemeier, Benny Eitan, Carole Dulong, Eiichi Kowashi, Wolf Witt
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Publication number: 20120173549Abstract: A processing system may receive an example image for use in querying a collection of digital images. The processing system may use local and global feature descriptors to perform a content-based image comparison of the digital images with the example image, to automatically rank the digital images with respect to similarity to the example image. A local feature descriptor may represent a portion of the contents of a digital image. A global feature descriptor may represent substantially all of the contents of that digital image. The global feature descriptor may be content based, not keyword based. Intermediate and final classifiers may be used to perform the automatic ranking. Different intermediate classifiers may generate intermediate relevance metrics with respect to different modalities. The final classifier may use results from the intermediate classifiers to produce a final relevance metric for the digital images. Other embodiments are described and claimed.Type: ApplicationFiled: March 15, 2012Publication date: July 5, 2012Inventors: Jean-Yves Bouguet, Carole Dulong, Igor V. Kozintsev, Yi Wu, Ara V. Nefian
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Patent number: 8200027Abstract: An image retrieval program (IRP) may be used to query a collection of digital images. The IRP may include a mining module to use local and global feature descriptors to automatically rank the digital images in the collection with respect to similarity to a user-selected positive example. Each local feature descriptor may represent a portion of an image based on a division of that image into multiple portions. Each global feature descriptor may represent an image as a whole. A user interface module of the IRP may receive input that identifies an image as the positive example. The user interface module may also present images from the collection in a user interface in a ranked order with respect to similarity to the positive example, based on results of the mining module. Query concepts may be saved and reused. Other embodiments are described and claimed.Type: GrantFiled: November 23, 2010Date of Patent: June 12, 2012Assignee: Intel CorporationInventors: Jean-Yves Bouguet, Carole Dulong, Igor V. Kozintsev, Yi Wu, Ara V. Nefian
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Patent number: 8185571Abstract: A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.Type: GrantFiled: March 23, 2009Date of Patent: May 22, 2012Assignee: Intel CorporationInventors: Alexander D. Peleg, Millind Mittal, Larry M. Mennemeier, Benny Eitan, Carole Dulong, Eiichi Kowashi, Wolf Witt
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Publication number: 20110264895Abstract: A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.Type: ApplicationFiled: July 1, 2011Publication date: October 27, 2011Inventors: Alexander D. Peleg, Millind Mittal, Larry M. Mennemeier, Benny Eitan, Carole Dulong, Eiichi Kowashi, Wolf Witt