Patents by Inventor Caroline Benveniste

Caroline Benveniste has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8250265
    Abstract: A method of transmitting compressed data from a main memory to an input/output adaptor (IOA)/input/output processor (IOP), includes sending compressed memory directory information to the IOA/IOP and copying a content of the memory to the IOA/IOP using a direct memory access (DMA) operation, without decompressing the data.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: August 21, 2012
    Assignee: International Business Machines Corporation
    Inventors: Caroline Benveniste, Vittorio Castelli, Peter A. Franaszek
  • Patent number: 8230139
    Abstract: In a computer system supporting memory compression, wherein memory compressed data is managed in units of memory sectors of size S, wherein data is stored on disk in a different compressed format, and wherein data on said disk is managed in units of disk sectors of size D, a method for storing memory compressed data on a compressed disk includes combining at least one of compressed memory directory information, a system header, compressed data controls, and pads into a data structure having a same size S as a memory sector, grouping the data structure and the data contained in the desired memory sectors into groups of D/S items, and storing each of the groups in a separate disk sector.
    Type: Grant
    Filed: January 30, 2012
    Date of Patent: July 24, 2012
    Assignee: International Business Machines Corporation
    Inventors: Caroline Benveniste, Vittorio Castelli, Peter A. Franaszek
  • Publication number: 20120131273
    Abstract: In a computer system supporting memory compression, wherein memory compressed data is managed in units of memory sectors of size S, wherein data is stored on disk in a different compressed format, and wherein data on said disk is managed in units of disk sectors of size D, a method for storing memory compressed data on a compressed disk includes combining at least one of compressed memory directory information, a system header, compressed data controls, and pads into a data structure having a same size S as a memory sector, grouping the data structure and the data contained in the desired memory sectors into groups of D/S items, and storing each of the groups in a separate disk sector.
    Type: Application
    Filed: January 30, 2012
    Publication date: May 24, 2012
    Applicant: IBM Corporation
    Inventors: Caroline Benveniste, Vittorio Castelli, Peter A. Franaszek
  • Patent number: 8161206
    Abstract: In a computer system supporting memory compression and wherein data is stored on a disk in a different compressed format, and wherein an IOA (input/output adaptor)/IOP (input/output processor) selectively reads from and writes to a main memory through a direct memory access (DMA) operation, a method for transmitting compressed data from the IOA/IOP to the main memory includes reserving a set of free memory sectors to contain the data in said main memory, sending to the IOA/IOP addresses of said memory sectors, copying the data from the IOA/IOP to said memory sectors using said DMA operation, constructing at the IOA/IOP compressed memory directory information defining how and where the data is stored in memory, sending the memory directory information to a memory controller, and storing the memory directory information in the compressed memory directory structure.
    Type: Grant
    Filed: April 8, 2011
    Date of Patent: April 17, 2012
    Assignee: International Business Machines Corporation
    Inventors: Caroline Benveniste, Vittorio Castelli, Peter A. Franaszek
  • Publication number: 20110185132
    Abstract: In a computer system supporting memory compression and wherein data is stored on a disk in a different compressed format, and wherein an IOA (input/output adaptor)/IOP (input/output processor) selectively reads from and writes to a main memory through a direct memory access (DMA) operation, a method for transmitting compressed data from the IOA/IOP to the main memory includes reserving a set of free memory sectors to contain the data in said main memory, sending to the IOA/IOP addresses of said memory sectors, copying the data from the IOA/IOP to said memory sectors using said DMA operation, constructing at the IOA/IOP compressed memory directory information defining how and where the data is stored in memory, sending the memory directory information to a memory controller, and storing the memory directory information in the compressed memory directory structure.
    Type: Application
    Filed: April 8, 2011
    Publication date: July 28, 2011
    Applicant: IBM Corporation
    Inventors: Caroline Benveniste, Vittorio Castelli, Peter A. Franaszek
  • Publication number: 20110179197
    Abstract: A method of transmitting compressed data from a main memory to an input/output adaptor (IOA)/input/output processor (IOP), includes sending compressed memory directory information to the IOA/IOP and copying a content of the memory to the IOA/IOP using a direct memory access (DMA) operation, without decompressing the data.
    Type: Application
    Filed: March 31, 2011
    Publication date: July 21, 2011
    Applicant: IBM Corporation
    Inventors: Caroline Benveniste, Vittorio Castelli, Peter A. Franaszek
  • Patent number: 7979602
    Abstract: A method (and system) of storing information, includes storing main memory compressed information onto a memory compressed disk, where pages are stored and retrieved individually, without decompressing the main memory compressed information.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: July 12, 2011
    Assignee: International Business Machines Corporation
    Inventors: Caroline Benveniste, Vittorio Castelli, Peter A. Franaszek
  • Patent number: 7958289
    Abstract: A method (and system) of storing information, includes storing main memory compressed information onto a memory compressed disk, where pages are stored and retrieved individually, without decompressing the main memory compressed information.
    Type: Grant
    Filed: August 8, 2002
    Date of Patent: June 7, 2011
    Assignee: International Business Machines Corporation
    Inventors: Caroline Benveniste, Vittorio Castelli, Peter A. Franaszek
  • Publication number: 20090313398
    Abstract: A method (and system) of storing information, includes storing main memory compressed information onto a memory compressed disk, where pages are stored and retrieved individually, without decompressing the main memory compressed information.
    Type: Application
    Filed: August 20, 2009
    Publication date: December 17, 2009
    Applicant: International Business Machines Corporation
    Inventors: Caroline Benveniste, Vittorio Castelli, Peter A. Franaszek
  • Patent number: 7103722
    Abstract: A method and structure is disclosed for constraining cache line replacement that processes a cache miss in a computer system. The invention contains a K-way set associative cache that selects lines in the cache for replacement. The invention constrains the selecting process so that only a predetermined subset of each set of cache lines is selected for replacement. The subset has at least a single cache line and the set size is at least two cache lines. The invention may further select between at least two cache lines based upon which of the cache lines was accessed least recently. A selective enablement of the constraining process is based on a free space memory condition of a memory associated with the cache memory. The invention may further constrain cache line replacement based upon whether the cache miss is from a non-local node in a nonuniform-memory-access system. The invention may also process cache writes so that a predetermined subset of each set is known to be in an unmodified state.
    Type: Grant
    Filed: July 22, 2002
    Date of Patent: September 5, 2006
    Assignee: International Business Machines Corporation
    Inventors: Caroline Benveniste, Peter Franaszek, John T. Robinson, Charles Schulz
  • Patent number: 6795897
    Abstract: A computer system and corresponding method for supporting a compressed main memory includes a processor, a processor cache in signal communication with the processor, a memory controller in signal communication with the processor cache, a compression translation table entry register in signal communication with the processor cache and the memory controller, a compression translation table directory in signal communication with the compression translation table entry register, and a compressed main memory in signal communication with the memory controller wherein the memory controller manages the compressed main memory by storing entries of the compression translation table directory into the processor cache from the compression translation table entry register; where the corresponding method includes receiving a real address for a processor cache miss, finding a compression translation table address for the cache miss within the processor cache, if the cache miss is a cache write miss: decompressing the memor
    Type: Grant
    Filed: May 15, 2002
    Date of Patent: September 21, 2004
    Assignee: International Business Machines Corporation
    Inventors: Caroline Benveniste, Vittorio Castelli, Peter A. Franaszek
  • Publication number: 20040030813
    Abstract: A method (and system) of storing information, includes storing main memory compressed information onto a memory compressed disk, where pages are stored and retrieved individually, without decompressing the main memory compressed information.
    Type: Application
    Filed: August 8, 2002
    Publication date: February 12, 2004
    Applicant: International Business Machines Corporation
    Inventors: Caroline Benveniste, Vittorio Castelli, Peter A. Franaszek
  • Publication number: 20040015660
    Abstract: A method and structure is disclosed for constraining cache line replacement that processes a cache miss in a computer system. The invention contains a K-way set associative cache that selects lines in the cache for replacement. The invention constrains the selecting process so that only a predetermined subset of each set of cache lines is selected for replacement. The subset has at least a single cache line and the set size is at least two cache lines. The invention may further select between at least two cache lines based upon which of the cache lines was accessed least recently. A selective enablement of the constraining process is based on a free space memory condition of a memory associated with the cache memory. The invention may further constrain cache line replacement based upon whether the cache miss is from a non-local node in a nonuniform-memory-access system. The invention may also process cache writes so that a predetermined subset of each set is known to be in an unmodified state.
    Type: Application
    Filed: July 22, 2002
    Publication date: January 22, 2004
    Inventors: Caroline Benveniste, Peter Franaszek, John T. Robinson, Charles Schulz
  • Publication number: 20030217237
    Abstract: A computer system and corresponding method for supporting a compressed main memory includes a processor, a processor cache in signal communication with the processor, a memory controller in signal communication with the processor cache, a compression translation table entry register in signal communication with the processor cache and the memory controller, a compression translation table directory in signal communication with the compression translation table entry register, and a compressed main memory in signal communication with the memory controller wherein the memory controller manages the compressed main memory by storing entries of the compression translation table directory into the processor cache from the compression translation table entry register; where the corresponding method includes receiving a real address for a processor cache miss, finding a compression translation table address for the cache miss within the processor cache, if the cache miss is a cache write miss: decompressing the memor
    Type: Application
    Filed: May 15, 2002
    Publication date: November 20, 2003
    Applicant: Internation Business Machines Corporation
    Inventors: Caroline Benveniste, Vittorio Castelli, Peter A. Franaszek