Abstract: An underfill device and method have been are provided. Advantages of devices and methods shown include dissipation of stresses at an interface between components such as a chip package and an adjacent circuit board. Another advantage includes faster manufacturing time and ease of manufacture using underfill devices and methods shown. An underfill assembly can be pre made with conductive structures included within the underfill assembly. Steps such as flowing epoxy and curing can be eliminated or performed concurrently with other manufacturing steps.

Abstract: An underfill device and method have been are provided. Advantages of devices and methods shown include dissipation of stresses at an interface between components such as a chip package and an adjacent circuit board. Another advantage includes faster manufacturing time and ease of manufacture using underfill devices and methods shown. An underfill assembly can be pre made with conductive structures included within the underfill assembly. Steps such as flowing epoxy and curing can be eliminated or performed concurrently with other manufacturing steps.

Abstract: An underfill device and method have been are provided. Advantages of devices and methods shown include dissipation of stresses at an interface between components such as a chip package and an adjacent circuit board. Another advantage includes faster manufacturing time and ease of manufacture using underfill devices and methods shown. An underfill assembly can be pre made with conductive structures included within the underfill assembly. Steps such as flowing epoxy and curing can be eliminated or performed concurrently with other manufacturing steps.

Abstract: An IC package is disclosed that comprises a core region disposed between upper and lower build-up layer regions. In one embodiment, the core region comprises a low modulus material. In an alternative embodiment the core region comprises a medium modulus material. In an alternative embodiment, the core material is selected based upon considerations such as it modulus, its coefficient of thermal expansion, and/or the resulting total accumulated strain. In an alternative embodiment, boundaries with respect to the softness of the core material are established be considering the reflective density in opposing conductive build-up layers above and below the core region.

Abstract: An IC package is disclosed that comprises a core region disposed between upper and lower build-up layer regions. In one embodiment, the core region comprises a low modulus material. In an alternative embodiment the core region comprises a medium modulus material. In an alternative embodiment, the core material is selected based upon considerations such as its modulus, its coefficient of thermal expansion, and/or the resulting total accumulated strain. In an alternative embodiment, boundaries with respect to the softness of the core material are established by considering the relative density in opposing conductive build-up layers above and below the core region.

Abstract: A protective coating of insulating material is formed around a clearance hole in a conductive layer of a printed circuit board, so that the conductive material in a via within the clearance hole will not contact the conductive layer and create a short circuit. In one embodiment, the protective coating is sufficiently hard to deflect a drill bit being used to drill the via hole, thus protecting against misregistered drilled holes.

Abstract: Methods to shield conductive layer from via. A protective coating of insulating material is formed around a clearance hole in a conductive layer of a printed circuit board, so that the conductive material in a via within the clearance hole will not contact the conductive layer and create a short circuit. In one embodiment, the protective coating is sufficiently hard to deflect a drill bit being used to drill the via hole, thus protecting against misregistered drilled holes.

Abstract: According to a method of mounting electronic components on a printed circuit board (PCB), the electrical contacts of the components are coupled to PCB bonding pads that are intersected by via pads. To minimize various defects encountered during solder reflow, while concurrently minimizing PCB area and manufacturing costs, the via pads are formed so that the via holes substantially avoid underlying the solder fillets coupling the component contacts to the PCB bonding pads. In one embodiment, the via pads are formed in the inter-pad space beneath the component; in another embodiment they are offset from the bonding pads. A substrate, an electronic assembly, and an electronic system are also described.

Abstract: Apparatus and methods for interconnecting a SMT component interconnect to a via-in-pad (VIP) interconnect. A first reflowable material is deposited on the VIP bond pad. A sphere having a higher melt temperature than the reflow temperature of the first interconnect material is deposited on the first interconnect material. A first reflow process is performed to interconnect the sphere and the VIP bond pad while the sphere remains solid, and the first reflowable material preventing the first interconnect material from migrating into the via-in-pad.

Abstract: A protective coating of insulating material is formed around a clearance hole in a conductive layer of a printed circuit board, so that the conductive material in a via within the clearance hole will not contact the conductive layer and create a short circuit. In one embodiment, the protective coating is sufficiently hard to deflect a drill bit being used to drill the via hole, thus protecting against misregistered drilled holes.

Abstract: Apparatus and methods providing for interconnecting a SMT component interconnect to a via-in-pad (VIP) interconnect is presented. In one embodiment in accordance with the invention, a first reflowable electrically conductive interconnect material is deposited on the VIP bond pad. A sphere comprising an electrically conductive material having a higher melt temperature than the reflow temperature of the first interconnect material is deposited on the first interconnect material. A first reflow process is performed to interconnect the sphere and the VIP bond pad while the sphere remains solid. A second electrically conductive interconnect material having a reflow temperature lower than the melt temperature of the sphere is deposited on the component interconnect and a second reflow process is performed to interconnect the sphere to the component interconnect while the sphere remains solid, effectively preventing the second interconnect material from migrating into the plated though hole.

Abstract: A first signal routing layer may be formed on a first surface of a printed circuit board (PCB). An array of interconnections may formed on the first surface of the PCB, the array of interconnections comprising at least one padless via formed within the PCB, the at least one padless via extending from the first signal routing layer to at least one conductive plane and/or a second signal routing layer. The at least one padless via may be in electrical contact with the at least one conductive plane and/or a conductive trace on the second signal routing layer. A component may be attached to the PCB, with a solder interconnection between the at least one padless via and a contact pad on a bottom surface of the component. The component may be, for example, an electronic component such as a ball grid array (BGA) component or a leadless surface mount component.

Abstract: A first signal routing layer may be formed on a first surface of a printed circuit board (PCB). An array of interconnections may formed on the first surface of the PCB, the array of interconnections comprising at least one padless via formed within the PCB, the at least one padless via extending from the first signal routing layer to at least one conductive plane and/or a second signal routing layer. The at least one padless via may be in electrical contact with the at least one conductive plane and/or a conductive trace on the second signal routing layer. A component may be attached to the PCB, with a solder interconnection between the at least one padless via and a contact pad on a bottom surface of the component. The component may be, for example, an electronic component such as a ball grid array (BGA) component or a leadless surface mount component.

Abstract: A first signal routing layer may be formed on a first surface of a printed circuit board (PCB). An array of interconnections may formed on the first surface of the PCB, the array of interconnections comprising at least one padless via formed within the PCB, the at least one padless via extending from the first signal routing layer to at least one conductive plane and/or a second signal routing layer. The at least one padless via may be in electrical contact with the at least one conductive plane and/or a conductive trace on the second signal routing layer. A component may be attached to the PCB, with a solder interconnection between the at least one padless via and a contact pad on a bottom surface of the component. The component may be, for example, an electronic component such as a ball grid array (BGA) component or a leadless surface mount component.

Abstract: An apparatus that includes a substrate, one or more via in pads in the substrate; and one or more vents in at least one of the one or more via in pads, the one or more vents connecting an outer diameter of at least one of the one or more via in pads to a diameter larger than the via.

Abstract: According to a method of mounting electronic components on a printed circuit board (PCB), the electrical contacts of the components are coupled to PCB bonding pads that are intersected by via pads. To minimize various defects encountered during solder reflow, while concurrently minimizing PCB area and manufacturing costs, the via pads are formed so that the via holes substantially avoid underlying the solder fillets coupling the component contacts to the PCB bonding pads. In one embodiment, the via pads are formed in the inter-pad space beneath the component; in another embodiment they are offset from the bonding pads. A substrate, an electronic assembly, and an electronic system are also described.

Abstract: A protective coating of insulating material is formed around a clearance hole in a conductive layer of a printed circuit board, so that the conductive material in a via within the clearance hole will not contact the conductive layer and create a short circuit. In one embodiment, the protective coating is sufficiently hard to deflect a drill bit being used to drill the via hole, thus protecting against misregistered drilled holes.

Abstract: An apparatus that includes a substrate, one or more via in pads in the substrate; and one or more vents in at least one of the one or more via in pads.

Abstract: To mount electronic components on a printed circuit board (PCB), the electrical contacts of the components are coupled to PCB bonding pads that are intersected by via pads. To minimize various defects encountered during solder reflow, while concurrently minimizing PCB area and manufacturing costs, the via pads are formed so that the via holes substantially avoid underlying the solder fillets coupling the component contacts to the PCB bonding pads. In one embodiment, the via pads are formed in the inter-pad space beneath the component; in another embodiment they are offset from the bonding pads. A substrate, an electronic assembly, and an electronic system are described.

Abstract: According to a method of mounting electronic components on a printed circuit board (PCB), the electrical contacts of the components are coupled to PCB bonding pads that are intersected by via pads. To minimize various defects encountered during solder reflow, while concurrently minimizing PCB area and manufacturing costs, the via pads are formed so that the via holes substantially avoid underlying the solder fillets coupling the component contacts to the PCB bonding pads. In one embodiment, the via pads are formed in the inter-pad space beneath the component; in another embodiment they are offset from the bonding pads. A substrate, an electronic assembly, and an electronic system are also described.