Abstract: Briefly, a method, apparatus and system for managing power corresponding to a differential serial communication link that has a link width defined for example by one or more lanes wherein the lanes are adapted to communicate clock recovery information in a data stream, determines, during normal operating conditions, such as conditions other than power on, reset or link fault conditions, a desired link width for the serial communication link and then changes the link width accordingly.

Abstract: Briefly, a method, apparatus and system for managing power corresponding to a differential serial communication link that has a link width defined for example by one or more lanes wherein the lanes are adapted to communicate clock recovery information in a data stream, determines, during normal operating conditions, such as conditions other than power on, reset or link fault conditions, a desired link width for the serial communication link and then changes the link width accordingly.

Abstract: A palette device controllable by a digital computer with a video memory to produce signals representing color for a video monitor. The palette device includes a multiple-bit input latch for entry of color codes from the video memory, and a look-up table memory for supplying color data words in response to color codes from the input latch. A digital to analog converter responds to color data words to produce an analog color signal. Selection circuitry connected to the input latch and to the look-up table memory supplies the digital to analog converter either with a color data word supplied by the look-up table memory or with a color data word comprised of color codes from the input latch. Improved graphics computer systems, facsimile systems, printer systems and other systems and methods are also disclosed.

Abstract: A method for displaying grey-scale images at a desired grey scale resolution up to the visible limit on a display having a matrix of pixels, includes the steps of: defining a plurality of control matrices, each of said control matrices having a size and equal to the desired grey scale resolution of the display, each position in each of said control matrices corresponding to a specific pixel of said display; defining a super matrix, each position in said super matrix corresponding to one of said plurality of control matrices and having an assigned number in a range equal to the desired grey scale resolution; turning on a selected number of pixels within each of said control matrices based upon the grey scale value of the pixel, the orientation of the pixels turned on based on the value of a circular queue of size equal to said desired gray scale resolution; and adjusting the starting value of said circular queue for each of said control matrices based upon the number contained in the position of the super matr

Abstract: A method for displaying grey-scale images at a desired grey scale resolution on a display having a matrix of pixels, comprises the steps of: defining a control matrix having a size smaller than the entire display and equal to the desired grey scale resolution of the display, each position in the control matrix having an address assigned such that unintended artifacts in the display are controlled; horizontally and vertically mapping the control matrix into the display such that each pixel in the matrix of pixels in the display corresponds to an address in a control matrix mapped into the display; comparing control matrix address of each pixel in a frame of an image to be displayed on the display to a range of address values and turning that pixel on if the grey scale value of that pixel is within the range of address values, the range of address values arranged in a circular queue and being equal to the grey scale value of that pixel; and shifting the range of address values in the circular queue for successi

Abstract: A color palette selects a master clock from plural clock signals received at clock input terminals in response to a master clock selection control word received at control data terminals. A circuit forms a plurality of divided down clock signals from selected divide ratios of the master clock. A circuit selects a shift clock from among the divided down clock signals in response to at least some bits of an output clock selection control word received at the control data terminals. A circuit selectively enables and disables the shift clock in response to blanking data. A circuit selects a video clock from among the divided down clock signals in response to at least some bits of the output clock selection control word. A circuit synchronizes multiple bit words of color code received at color code input terminals with the master clock. A circuit outputs at least one memory recall address in response to receiving each multiple bit word of color code.

Abstract: A palette device controllable by a digital computer with a video memory having a bus for supplying multiple color codes for the palette device in each bus cycle. The palette device includes a multiple-bit input for entry of the color codes from the bus, and a look-up table memory for supplying color data words in response to the color codes from the input. Color code transfer circuitry is connected between the input and the look-up table memory to supply the look-up table memory from the input sequentially with color codes of selectable width packing the entire width of the bus. Improved palette devices, graphics computer systems, facsimile systems, printer systems and other systems and methods are also disclosed.

Abstract: An integrated circuit for use with a plurality of clock oscillators. The integrated circuit has a semiconductor chip, function performing circuitry fabricated on the semiconductor chip and responsive to clock pulses provided thereto, and a semiconductor chip package having pins connected to the function performing circuitry. The integrated circuit further has a register accessible via the pins for external entry of clock control information. A clock control circuit responsive to the clock control information entered in said register has inputs connected to pins for the clock oscillators. The function performing circuitry is connected to the clock control circuit so that clock pulses are provided to the function performing circuitry by the clock control circuit in accordance with the clock control information entered in the register. Other integrated circuits, palette devices, computer graphics systems, printer systems and methods are also disclosed.

Abstract: A palette device responsive to color codes supplied on a bus and for producing signals representing color for a color display device. The palette device includes a plurality of look-up table memories each for supplying color data words in response to color codes supplied to access the memories respectively and a plurality of digital to analog converters respectively connected to said plurality of look-up table memories and responsive to the respective color data words from the memories to produce a plurality of analog color signals. A splitter circuit is provided for connection to the bus and is connected at a plurality of outputs thereof to access each of the look-up table memories concurrently. Other palette devices, computer graphics systems, facsimile systems, printer systems and methods are also disclosed.