Abstract: Aligning FIFO pointers includes resetting, by a write control block coupled to a write side of the FIFO, write pointers to an initial value. Then, iteratively, until one or more bits retrieved from the write side match one or more bits of an alignment bit pattern: providing, by the write side to the read side, the alignment bit pattern; retrieving, by the read side, one or more bits from the write side; providing, by the read side through a read control block, the retrieved one or more bits to the write control block; determining, by the write control block, whether the retrieved one or more bits match one or more bits of the alignment bit pattern; and, if the retrieved one or more bits do not match one or more bits of the alignment bit pattern, suppressing the read pointer from incrementing for a predetermined period of time.

Abstract: A Decision Feedback Equalizer (‘DFE’) that includes: a plurality of input signal lines comprising at least one data signal line and a plurality of power control signal lines; at least one output signal line; and a plurality of independently-controlled isolated power domains, where each independently-controlled isolated power domain is coupled to a corresponding one of the power control signal lines, each of the power control signal lines configured to transmit a power control signal to the independently-controlled isolated power domain dynamically, and each independently-controlled isolated power domain selectively consumes power in response to the power control signal, each independently-controlled isolated power domain configured to be dynamically powered up or powered down without impacting signal processing operations.

Abstract: Aligning FIFO pointers includes resetting, by a write control block coupled to a write side of the FIFO, write pointers to an initial value. Then, iteratively, until one or more bits retrieved from the write side match one or more bits of an alignment bit pattern: providing, by the write side to the read side, the alignment bit pattern; retrieving, by the read side, one or more bits from the write side; providing, by the read side through a read control block, the retrieved one or more bits to the write control block; determining, by the write control block, whether the retrieved one or more bits match one or more bits of the alignment bit pattern; and, if the retrieved one or more bits do not match one or more bits of the alignment bit pattern, suppressing the read pointer from incrementing for a predetermined period of time.

Abstract: Methods and apparatuses for adaptable receiver detection are provided. Embodiments include providing, by receiver detection circuitry at a transmitter coupled to a communication link, a voltage to the communication link; determining, by the receiver detection circuitry, a rise time corresponding to a rising edge change of the voltage on the communication link; determining, by the receiver detection circuitry, a fall time corresponding to a falling edge change of the voltage on the communication link; and determining, by the receiver detection circuitry, whether the rise time and the fall time are consistent with the transmitter being coupled through the communication link to a remote receiver.

Abstract: Aspects of the invention provide for an ESD protection device for an SST transmitter. In one embodiment, the ESD protection device includes: a primary ESD protection structure at an output of the SST transmitter; and an additional protection ESD structure in parallel with a slice of the SST transmitter, the additional ESD protection structure including: a first device in parallel with a pull-up transistor network within the slice; and a second device in parallel with a pull-down transistor network within the slice.

Abstract: A Decision Feedback Equalizer (DFE) that includes: a plurality of input signal lines comprising at least one data signal line and a plurality of power control signal lines; at least one output signal line; and a plurality of independently-controlled isolated power domains, where each independently-controlled isolated power domain is coupled to a corresponding one of the power control signal lines, each of the power control signal lines configured to transmit a power control signal to the independently-controlled isolated power domain dynamically, and each independently-controlled isolated power domain selectively consumes power in response to the power control signal, each independently-controlled isolated power domain configured to be dynamically powered up or powered down without impacting signal processing operations.

Abstract: Dual-loop voltage regulator circuits and methods in which a dual-loop voltage regulation framework is implemented with a first inner loop having a bang-bang voltage regulator to achieve nearly instantaneous response time, and a second outer loop, which is slower in operating speed than the first inner loop, to controllably adjust a trip point of the bang-bang voltage regulator to achieve high DC accuracy.

Abstract: Methods and apparatuses for adaptable receiver detection are provided. Embodiments include providing, by receiver detection circuitry at a transmitter coupled to a communication link, a voltage to the communication link; determining, by the receiver detection circuitry, a rise time corresponding to a rising edge change of the voltage on the communication link; determining, by the receiver detection circuitry, a fall time corresponding to a falling edge change of the voltage on the communication link; and determining, by the receiver detection circuitry, whether the rise time and the fall time are consistent with the transmitter being coupled through the communication link to a remote receiver.

Abstract: Aspects of the invention provide for an ESD protection device for an SST transmitter. In one embodiment, the ESD protection device includes: a primary ESD protection structure at an output of the SST transmitter; and an additional protection ESD structure in parallel with a slice of the SST transmitter, the additional ESD protection structure including: a first device in parallel with a pull-up transistor network within the slice; and a second device in parallel with a pull-down transistor network within the slice.

Abstract: A source-series terminated (‘SST’) driver circuit that includes: one or more data signal inputs; one or more control signal inputs; a driver output; and a plurality of driver cells, the driver cells coupled in parallel to one another, outputs of the driver cells coupled together to form the driver output of the SST driver circuit, where output resistance of the SST driver circuit varies in dependence upon activation of one or more of the parallel driver cells, activation of each driver cell controlled by control signals received at the control signal inputs.

Abstract: A source-series terminated (‘SST’) driver circuit that includes: one or more data signal inputs; one or more control signal inputs; a driver output; and a plurality of driver cells, the driver cells coupled in parallel to one another, outputs of the driver cells coupled together to form the driver output of the SST driver circuit, where output resistance of the SST driver circuit varies in dependence upon activation of one or more of the parallel driver cells, activation of each driver cell controlled by control signals received at the control signal inputs.

Abstract: Dual-loop voltage regulator circuits and methods in which a dual-loop voltage regulation framework is implemented with a first inner loop having a bang-bang voltage regulator to achieve nearly instantaneous response time, and a second outer loop, which is slower in operating speed than the first inner loop, to controllably adjust a trip point of the bang-bang voltage regulator to achieve high DC accuracy.

Abstract: A method for matching receiver and transmitter common-mode voltages for a high-speed direct current (DC) serial connection between the receiver and the transmitter includes measuring, at the receiver, a common-mode voltage of the transmitter. The common-mode voltage of the transmitter is an average of a voltage signal transmitted by the transmitter and received by the receiver. The method further includes comparing the common-mode voltage of the transmitter with a common-mode voltage of the receiver. The method further includes maintaining the common-mode voltage of the receiver at a first level at which the common-mode voltage of the receiver substantially matches the common-mode voltage of the transmitter.

Abstract: A high speed serial link structure and method are provided, comprising a data driver and a replica driver structure, the replica driver structure comprising a replica driver, a calibration engine and a peak level detector. The calibration engine compares a peak level detector output to a reference value and responsively performs a data driver adjustment, wherein the data driver adjustment comprises at least one of a driver biasing adjustment, a driver intermediate stage bandwidth adjustment and a driver equalization setting adjustment. In some embodiments, the calibration engine incorporates a comparator and a digital state machine; in other embodiments, it incorporates an analog operational amplifier.

Abstract: A method for manufacturing a calibration device for an active circuit on a chip, comprises: providing an active circuit that is capable of exhibiting a desired electrical characteristic; and providing a calibration mechanism on-chip with the active circuit. The calibration mechanism generates a control output and comprises a device under test (DUT) configured as a replica of at least one segment of the active circuit, and which generates a test output that causes finite adjustments to the control output, based on a comparison of the electrical characteristics exhibited by the DUT with a known electrical characteristic. The method further comprises: attaching to each control input terminal of the active circuit a corresponding control output from the calibration mechanism. The control output of the calibration mechanism dynamically adjusts control input applied to devices of the active circuit to force the active circuit to exhibit the desired electrical characteristic.

Abstract: Protection for the transmission of higher amplitude outputs required of differential amplifiers formed by thin oxide transistors with limited maximum voltage tolerance used where compliance with communication protocol standards requires handling voltages which may, in transition, exceed desirable levels is provided by limiting the voltage across any two device terminals under power down conditions.

Abstract: Substantially-accurate calibration of output impedance of a device-under-test (DUT) to within a predetermined range of allowable impedance. The DUT is part of a source series terminated (SST) serial link transmitter, in which two branches of parallel transistors each provide an impedance value when particular transistors of the parallel branch are turned on. The impedance value is added to a series-connected resistor to provide the output impedance. The DUT consists of one branch of parallel transistors in series with a resistor. Output impedance of the DUT is compared to the resistance of a reference resistor, and the comparator provides a control signal based on whether the output impedance falls within the pre-set percentage variance of the reference resistance. The control signal is processed by a FSM (finite state machine) that individually turns on or off the transistors within the parallel branch until the DUT impedance value falls within the desired range.

Abstract: A method for matching receiver and transmitter common-mode voltages for a high-speed direct current (DC) serial connection between the receiver and the transmitter includes measuring, at the receiver, a common-mode voltage of the transmitter. The common-mode voltage of the transmitter is an average of a voltage signal transmitted by the transmitter and received by the receiver. The method further includes comparing the common-mode voltage of the transmitter with a common-mode voltage of the receiver. The method further includes maintaining the common-mode voltage of the receiver at a first level at which the common-mode voltage of the receiver substantially matches the common-mode voltage of the transmitter.

Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for protection for the transmission of higher amplitude outputs required of differential amplifiers formed by thin oxide transistors with limited maximum voltage tolerance used where compliance with communication protocol standards requires handling voltages which may, in transition, exceed desirable levels is provided by limiting the voltage across any two device terminals under power down conditions.

Abstract: An (SST) driver circuit having additional circuitry for minimizing data-dependent jitter in the SST driver and increasing frequency amplitude in the SST driver. The additional circuity comprises a plurality of switches configured to be turned on or pulsed on momentarily during operation to discharge a node in the SST output stage for the purpose of removing the stored charge before the next transition cycle of the output stage.